AP0100CS datasheet(46/73 Pages) ONSEMI

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AP0100CS HDR: Image Signal Processor (ISP)

Protocol

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

Sequential READ, Start from Current Location

This sequence (Figure 35) starts in the same way as the single READ from current loca-

tion (Figure 33). Instead of generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge bit and continues to

perform byte reads until “L” bytes have been read.

Figure 35:

Sequential READ, Start from Current Location

Single Write to Random Location

Figure 36 shows the typical WRITE cycle from the host to the AP0100CS.The first 2 bytes

indicate a 16-bit address of the internal registers with most-significant byte first. The

following 2 bytes indicate the 16-bit data.

Figure 36:

Single WRITE to Random Location

Read Data

Previous Reg Address, N

N+1

N+2

N+L-1

N+L

Read Data

Slave Address

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Slave Address

A Reg Address[15:8]

Reg Address[7:0]

Previous Reg Address, N

Reg Address, M

M+1

Write Data

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