AP0100CS datasheet(45/73 Pages) ONSEMI

45 / 73 page

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Protocol

Single READ from Random Location

Figure 32 shows the typical READ cycle of the host to the AP0100CS. The first two bytes

sent by the host are an internal 16-bit register address. The following 2-byte READ cycle

sends the contents of the registers to host.

Figure 32:

Single READ from Random Location

Single READ from Current Location

Figure 33 shows the single READ cycle without writing the address. The internal address

will use the previous address value written to the register.

Figure 33:

Single Read from Current Location

Sequential READ, Start from Random Location

This sequence (Figure 34) starts in the same way as the single READ from random loca-

tion (Figure 32 on page 45). Instead of generating a no-acknowledge bit after the first

byte of data has been transferred, the master generates an acknowledge bit and

continues to perform byte READs until “L” bytes have been read.

Figure 34:

Sequential READ, Start from Random Location

S = start condition

P = stop condition

Sr = restart condition

A = acknowledge

A = no-acknowledge

slave to master

master to slave

Slave Address

A Reg Address[15:8]

Reg Address[7:0]

Slave Address

Read Data

[15:8]

Previous Reg Address, N

Reg Address, M

M+1

Read Data

[7:0]

Slave Address

Read Data

[15:8]

Slave Address

Read Data

[15:8]

Previous Reg Address, N

Reg Address, N+1

N+2

Read Data

[7:0]

Read Data

[7:0]

Read Data

(15:8)

Read Data

(15:8)

Read Data

(7:0)

Slave Address

A Reg Address[15:8] A

Reg Address[7:0] A

Read Data

Slave Address

Previous Reg Address, N

Reg Address, M

M+1

M+2

M+1

M+3

M+L-2

M+L-1

M+L

A P

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(7:0)

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