TPS2140IPWPR datasheet(9/33 Pages) TI1

9 / 33 page

TPS2140, TPS2141

TPS2150, TPS2151

SLVS399A − JANUARY 2002 − REVISED MAY 2006

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electrical characteristics over recommended operating junction temperature range,

VI(SW_IN) = 3.3 V for TPS2140/50, VI(SW_IN) = 5 V for TPS2141/51, VI(LDO_IN) =5V, all outputs unloaded

(unless otherwise noted) (continued)

adjustable voltage regulator (Vset = 0.9 V to 3.3 V)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VO(LDO_OUT)

Output voltage total tolerance

VI(LDO_IN) = Vset + 0.6 V to 5.5 V and

VI(LDO_IN)> 2.7 V, IO(LDO_OUT) = 5 mA to

250 mA

−4%

VO(LDO_OUT)

Line regulation

VI(LDO_IN) = VO(LDO_OUT) + 0.6 V to 5.5 V and

VI(LDO_IN)> 2.7 V, IO(LDO_OUT) = 5 mA

0.03

0.1

%/V

VO(LDO_OUT)

Load regulation

VI(LDO_IN)=VO(LDO_OUT) + 0.6 V to 5.5 V and

VI(LDO_IN)> 2.7 V, IO(LDO_OUT) = 5 mA to

250 mA ( a percentage of Vset)

0.6%

1.3%

VSET

Regulated output voltage set

range

VI(LDO_IN) ≥ VO(LDO_OUT) + 0.6 V

VI(LDO_IN) ≥ 2.7 V, IO(LDO_OUT) = 0 mA to

250 mA

0.9

3.3

Vref

ADJ reference voltage

0.8

VDROP

Drop-out voltage

VI(LDO_IN) – VSET = −0.1 V,

IO(LDO_OUT) = 250 mA

0.18

0.5

PSRR

Power supply rejection ratio,

20 log(Vac/Vo)‡

Vac = 1 kHz sine wave, 100 mVpp

superimposed on LDO_IN, CL = 4.7 µF,

ESR = 0.25

Ω, IO = 5 mA

LDO current limit

Short circuit peak current‡

LDO_OUT is enabled into a

short to ground

TJ = −40°C

to 110

°C

0.7

LDO current limit

Overload or short circuit dc

current limit

LDO_OUT is over-loaded or en-

abled into a short to ground

TJ = −40°C

to 110

°C

250

325

500

LDO forward leakage

current ILK_LDO

Current into pin LDO_OUT

VO(LDO_OUT) = 0 V, VI(LDO_IN) = 5.5 V,

VI(EN_LDO) = 0 V

LDO reverse leakage

current IRLK_LDO

Current into pin LDO_OUT

VO(LDO_OUT) = 5.5 V, VI(LDO_IN) = 0 V,

VI(EN_LDO) = 0 V

µA

tON_LDO

Turnon time

From 50% VI(EN_LDO) to 90% VO(LDO_OUT),

RL = VO(LDO_OUT)/0.2, CL = 10 µF (20%)

0.1

0.35

tOFF_LDO

Turnoff time

From 50% VI(EN_LDO) to 10% VO(LDO_OUT),

RL = VO(LDO_OUT)/0.2, CL = 10 µF (20%)

0.1

0.4

VO(LDO_OUT) ramp-up time (0%

to 90%)

VI(EN_LDO) = 5V, VI(LDO_IN) ramping up from

10% to 90% in 0.1 ms, RL = VO(LDO_OUT)/0.2,

CL = 10 µF (20%)

0.1

0.65

LDO pulldown transistor current

VI(PLDN_LDO) = 3.3 V

LDO pulldown transistor current

VI(LDO_PLDN) = 1 V

‡ Not tested in production.

undervoltage lockout, LDO_IN

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LDO UVLO rising threshold

2.7

LDO UVLO falling threshold

2.25

2.45

UVLO hysteresis‡

250

‡ Not tested in production.

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