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TMS570LS3134 bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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TMS570LS3134 bảng dữ liệu(HTML) 6 Page - Texas Instruments |
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6 / 167 page  TMS570LS3134, TMS570LS2134, TMS570LS2124 SPNS165B – APRIL 2012 – REVISED MAY 2015 www.ti.com Table of Contents 1 Device Overview ......................................... 1 6.12 Parity Protection for Peripheral RAMs .............. 81 1.1 Features .............................................. 1 6.13 On-Chip SRAM Initialization and Testing ........... 83 1.2 Applications ........................................... 2 6.14 External Memory Interface (EMIF) .................. 85 1.3 Description ............................................ 3 6.15 Vectored Interrupt Manager ......................... 92 1.4 Functional Block Diagram ............................ 5 6.16 DMA Controller ...................................... 95 2 Revision History ......................................... 7 6.17 Real Time Interrupt Module ......................... 97 3 Device Comparison ..................................... 9 6.18 Error Signaling Module .............................. 99 4 Terminal Configuration and Functions ........... 10 6.19 Reset / Abort / Error Sources ...................... 103 4.1 ZWT BGA Package Ball-Map (337-Ball Grid Array) 11 6.20 Digital Windowed Watchdog ....................... 105 4.2 Terminal Functions ................................. 12 6.21 Debug Subsystem ................................. 106 5 Specifications .......................................... 39 7 Peripheral Information and Electrical Specifications ......................................... 117 5.1 Absolute Maximum Ratings ........................ 39 7.1 Peripheral Legend ................................. 117 5.2 ESD Ratings ........................................ 39 7.2 Multibuffered 12-Bit Analog-to-Digital Converter .. 117 5.3 Power-On Hours (POH) ............................. 39 7.3 General-Purpose Input/Output ..................... 128 5.4 Recommended Operating Conditions ............... 40 7.4 Enhanced Next Generation High-End Timer 5.5 Switching Characteristics for Clock Domains ....... 41 (N2HET) ............................................ 129 5.6 Wait States Required ............................... 41 7.5 Controller Area Network (DCAN) .................. 134 5.7 Power Consumption ................................. 42 7.6 Local Interconnect Network Interface (LIN) ........ 135 5.8 Input/Output Electrical Characteristics .............. 43 7.7 Serial Communication Interface (SCI) ............. 136 5.9 Thermal Resistance Characteristics ................ 44 7.8 Inter-Integrated Circuit (I2C) ....................... 137 5.10 Output Buffer Drive Strengths ...................... 45 7.9 Multibuffered / Standard Serial Peripheral 5.11 Input Timings ........................................ 46 Interface ............................................ 140 5.12 Output Timings ...................................... 46 8 Device and Documentation Support .............. 152 5.13 Low-EMI Output Buffers ............................ 48 8.1 Device Support ..................................... 152 6 System Information and Electrical 8.2 Documentation Support ............................ 154 Specifications ........................................... 50 8.3 Related Links ...................................... 154 6.1 Device Power Domains ............................. 50 8.4 Community Resources ............................. 154 6.2 Voltage Monitor Characteristics ..................... 51 8.5 Trademarks ........................................ 154 6.3 Power Sequencing and Power On Reset ........... 52 8.6 Electrostatic Discharge Caution ................... 154 6.4 Warm Reset (nRST) ................................. 54 8.7 Glossary ............................................ 154 6.5 ARM Cortex-R4F CPU Information ................. 55 8.8 Device Identification Code Register ............... 155 6.6 Clocks ............................................... 59 8.9 Die Identification Registers ....................... 156 6.7 Clock Monitoring .................................... 67 8.10 Module Certifications ............................... 157 6.8 Glitch Filters ......................................... 69 9 Mechanical Packaging and Orderable 6.9 Device Memory Map ................................ 70 Information ............................................. 162 6.10 Flash Memory ....................................... 78 9.1 Packaging Information ............................. 162 6.11 Tightly Coupled RAM (TCRAM) Interface Module .. 81 6 Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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