TMS320C6421 datasheet(70/222 Pages) TI1

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3.4.1.5 Host Boot Modes

3.4.2

Bootmode Registers

3.4.2.1 BOOTCFG Register

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346D – JANUARY 2007 – REVISED JUNE 2008

www.ti.com

For example, if BOOTMODE[3:0] = 0110b, FASTBOOT = 1, the MXI/CLKIN frequency = 30 MHz,

PLLMS[2:0] = 100b, the combination of Table 3-5 and Table 3-6 indicates that the device frequency

(SYSCLK1) is CLKIN x 22 / 2 = 330 MHz. This means SYSCLK3 frequency is 330 / 6 = 55 MHz, resulting

in SPI serial clock frequency of 55 / 3 = 18.3 MHz.

The C6421 supports HPI Boot.

The HPI Boot is available in fastboot and non-fastboot, as shown in Table 3-4 and Table 3-5.

Note: The HPI HSTROBE inactive pulse duration timing requirement [tw(HSTBH)] is dependent on the HPI

internal clock source (SYSCLK3) frequency (see Section 6.12.3, HPI Electrical Data/Timing). The external

host must be aware of the SYSCLK3 frequency during boot to ensure the HSTROBE pulse duration

timing requirement is met.

The Device Bootmode (see Section 3.4.1, Boot Modes) and Configuration pins (see Section 3.5.1, Device

and Peripheral Configurations at Device Reset) latched at reset are captured in the Device Boot

Configuration (BOOTCFG) register which is accessible through the System Module. This is a read-only

reset. For more information on how these pins are sampled at device reset, see Section 6.5.1.2, Latching

Boot and Configuration Pins. For the corresponding device boot and configuration pins, see Table 2-7,

BOOT Terminal Functions.

RESERVED

LENDIAN FASTBOOT

RESERVED

R-0000 0000 0001

R-L

R-000

RSV

PLLMS

RSV

DAEM

RESERVED

BOOTMODE

R-0

R-LLL

R-0

R-LLL

R-0000

R-LLLL

LEGEND: R = Read only; L = pin state latched at reset rising edge; -n = value after reset

Figure 3-2. BOOTCFG Register—0x01C4 0014

Table 3-7. BOOTCFG Register Description

Bit

Field Name

Description

31:21

RESERVED

Reserved. Writes have no effect.

Little Endian Selection (see Section 3.5.1.3, Endianess Selection (LENDIAN))

This field determines the device endian mode.

LENDIAN

0 = Device is Big Endian

1 = Device is Little Endian

The default value is latched from LENDIAN configuration pin.

Fastboot (see Section 3.4.1.1, FASTBOOT)

This field is used by the device bootloader code to determine if it needs to speed up the device to PLL mode

before booting.

FASTBOOT

0 = No Fastboot

1 = Fastboot

The default value is latched from FASTBOOT configuration pin.

18:15

RESERVED

Reserved. Writes have no effect.

Device Configurations

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