TMS320C6472ECTZ datasheet(246/269 Pages) TI1

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P48

1Fh

N+1

N+2

N+1

N+2

URCLK

(input)

URDATA[15:0]

(input)

URADDR[4:0]

(input)

URCLA

(output)

URENB

(input)

URSOC

(input)

1Fh

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

Table 7-146. Timing Requirements for UTOPIA Slave Receive Cycles

(see Figure 7-63)

500/625/700

NO.

UNIT

MIN

MAX

tsu(URDATA−URCLKH)

Setup time, URDATA valid before URCLK high

th(URCLKH−URDATA)

Hold time, URDATA valid after URCLK high

tsu(URADDR−URCLKH)

Setup time, URADDR valid before URCLK high

th(URCLKH−URADDR)

Hold time, URADDR valid after URCLK high

tsu(URENB−URCLKH)

Setup time, URENB valid before URCLK high

th(URCLKH−URENB)

Hold time, URENB valid after URCLK high

tsu(URSOC−URCLKH)

Setup time, URSOC valid before URCLK high

th(URCLKH−URSOC)

Hold time, URSOC valid after URCLK high

Table 7-147. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave

Receive Cycles

(see Figure 7-63)

500/625/700

NO.

PARAMETER

UNIT

MIN

MAX

13(1)

td(URCLKH−URCLAV)

Delay time, URCLK high to URCLAV valid

14(1)

ten(URCLKH−URCLAV)

Enable time, URCLK high to URCLAV driven

15(2) (3) tdis(URCLKL−URCLAVZ)

Disable time, URCLK low to URCLAV high-impedance state

(1)

MAX delay time and enable time increases to 12.5 ns at 20 pF and 14 ns at 30 pF, specified by design.

(2)

Specifed by design for MIN values.

(3)

Specifed by design for MAX values.

Figure 7-63. UTOPIA Slave Receive

246

C64x+ Peripheral Information and Electrical Specifications

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