TMS320C6472ECTZ datasheet(162/269 Pages) TI1

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PLLV2

CLKIN2

PLLCTL

PLLEN

SYSCLK13

/10,/4

SYSCLK14

/100

SYSCLK15

SYSCLK16

/10

SYSCLK17

/100

SYSCLK18

PLL2Controller

PLL2

PLLRST

PLLPWRDN

BypassMode

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

Figure 7-25. PLL2 and PLL2 Controller

Table 7-31. PLL2 Clock Frequency Ranges

CLOCK SIGNAL

REQUIRED FREQUENCY

UNIT

CLKIN2

MHz

SYSCLK13

250

MHz

SYSCLK14

50 or 125

MHz

SYSCLK15

MHz

SYSCLK16

250

MHz

SYSCLK17

MHz

SYSCLK18

MHz

7.9.1.2

PLL2 Controller

The PLL2 controller provides the control to reset PLL2. It is also capable of placing it in a power-down

condition for systems where Ethernet is not being used.

7.9.1.3

PLL2 Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after device powerup. The PLL should not be operated until this stabilization time has

expired. The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST =

1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For

the PLL2 reset time value, see Table 7-32. The PLL lock time is the amount of time needed from when the

PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when the PLL controller can be switched to PLL

mode (PLLEN=1). The PLL2 lock time is given in Table 7-32.

162

C64x+ Peripheral Information and Electrical Specifications

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