TMS320C6472ECTZ datasheet(151/269 Pages) TI1

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TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

Table 7-18. PLL1 Clock Frequency Ranges

REQUIRED FREQUENCY

CLOCK SIGNAL

UNIT

FOR 500-MHz OPERATION

FOR 625-MHz OPERATION

FOR 700-MHz OPERATION

CLKIN1

15.625 - 50.0

19.531 - 50.0

21.875 - 50.0

MHz

SYSCLK1

500.0

625.0

700.0

MHz

SYSCLK2

500.0

625.0

700.0

MHz

SYSCLK3

500.0

625.0

700.0

MHz

SYSCLK4

500.0

625.0

700.0

MHz

SYSCLK5

500.0

625.0

700.0

MHz

SYSCLK6

500.0

625.0

700.0

MHz

SYSCLK7

166.7

208.4

233.3

MHz

SYSCLK8

83.3

104.1

116.7

MHz

SYSCLK9

250.0

312.5

350.0

MHz

SYSCLK10

166.7(1)

208.4(1)

233.3(1)

MHz

(1)

This frequency may be changed by reprogramming SYSCLK10.

7.8.1.2

PLL1 Controller Operating Modes

The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is

determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is

generated from the device input clock, CLKIN1, using the the PLL multiplier, PLLM. In bypass mode,

CLKIN1 is fed directly to SYSREFCLK. All hosts (HPI, etc.) must hold off accesses to the DSP while the

frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the

host when the PLL configuration has completed.

The PLL3 controller provides the control to reset PLL3. It is also capable of placing it in a power-down

condition for systems where DDR2 EMIF is not being used.

7.8.1.3

PLL1 Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after device powerup. The PLL output should not be used until this stabilization time has

expired. The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST =

1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For

the PLL1 reset time value, see Table 7-19.The PLL lock time is the amount of time needed from when the

PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when the PLL controller can be switched to PLL

mode (PLLEN=1). The PLL1 lock time is given in Table 7-19.

Table 7-19. PLL1 Stabilization, Lock, and Reset Times

MIN

TYP

MAX

UNIT

PLL1 stabilization time

μs

PLL1 lock time

2000 * C(1)

PLL1 reset time

256 * C(1)

(1)

C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.

C64x+ Peripheral Information and Electrical Specifications

151

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