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UCD3138128APFC bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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UCD3138128APFC bảng dữ liệu(HTML) 11 Page - Texas Instruments |
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11 / 83 page ![]() 11 UCD3138128A www.ti.com SLUSC99 – JULY 2016 Product Folder Links: UCD3138128A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics (continued) V33A = V33D = V33DIO = 3 V to 3.6 V; 1 μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT (2) On the 40 pin package V33DIO is connected to V33D internally. (3) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH. (4) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset. Sample Rate(1) 15.62 5 MHz Analog Front End Amplifier Bandwidth(1) 100 MHz A0 Gain(1) See Figure 12 1 V/V Minimum output voltage 25 mV EADC DAC DAC range 0 1.6 V VREF DAC reference resolution 10 bit, No dithering enabled 1.56 mV VREF DAC reference resolution(1) With 4 bit dithering enabled 97.6 μV INL Guaranteed INL –1.5 1.5 LSB Typical INL (TJ =25°C, V33A = V33D = V33DIO = 3.3V) -0.4/+0.7 LSB DNL Guaranteed DNL –2.0 1 LSB Typical DNL (TJ =25°C, V33A = V33D = V33DIO = 3.3V) -0.4/+0.3 LSB DAC reference voltage 1.58 1.61 V ADC12 IBIAS Bias current for PMBus address pins 9.5 10.5 μA Measurement range for voltage monitoring 0 2.5 V Internal ADC reference voltage 2.475 2.500 2.525 V Change in Internal ADC reference from 25°C reference voltage(1) 25°C to -40°C -2.36 mV 25°C to 125°C -5.45 ADC12 INL integral nonlinearity, end point(1) ADC_SAMPLING_SEL = 0 or 7 for all ADC12 data -3.9 -2.5/2.2 4.5 LSB ADC12 INL integral nonlinearity, best fit line(1) -2.4 -1.6/1.7 2.9 LSB ADC12 DNL differential nonlinearity(1) -1.0 –0.6/+2.6 3.8 LSB ADC Zero Scale Error –5 5 mV ADC Full Scale Error –30 30 mV Input bias 2.5 V applied to pin 200 nA Input leakage resistance(1) ADC_SAMPLING_SEL = 0 2 M Ω ADC_SAMPLING_SEL = 7 1 M Ω Input Capacitance(1) 10 pF DIGITAL INPUTS/OUTPUTS(2) VOL Low-level output voltage(3)(4) IOH = 4 mA, V33DIO = 3 V DGND + 0.25 V VOH High-level output voltage (3) IOH = –4 mA, V33DIO = 3 V V33DIO – 0.6 V VIH High-level input voltage V33DIO = 3 V 2.1 V VIL Low-level input voltage V33DIO = 3 V 1.1 V IOH Output sinking current 4 mA IOL Output sourcing current –4 mA SYSTEM PERFORMANCE ISHARE Current share current source (See Figure 34) 238 259 μA |
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