TLV320DAC32 datasheet(39/70 Pages) TI1

39 / 70 page

TLV320DAC32

www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008

Page 0 / Register 4:

PLL Programming Register B

BIT

READ/

RESET

DESCRIPTION

WRITE

VALUE

D7–D2

R/W

000001

PLL J Value

000000: Reserved, do not write this sequence

000001: J = 1

000010: J = 2

000011: J = 3

…

111110: J = 62

111111: J = 63

D1–D0

R/W

Reserved, write only zeros to these bits

Table 1. Page 0 / Register 5:

PLL Programming Register C(1)

BIT

READ/

RESET

DESCRIPTION

WRITE

VALUE

D7-D0

R/W

00000000

PLL D(13:6) – Eight most significant bits of a 14-bit unsigned integer valid values for D are from

zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be

written into these registers that would result in a D value outside the valid range.

(1)

When programming PLL D value, register 5 should always be written first, immediately followed by register 6. Even if only the MSB or

LSB of the value changes, both registers should be written.

Page 0 / Register 6:

PLL Programming Register D

BIT

READ/

RESET

DESCRIPTION

WRITE

VALUE

D7–D2

R/W

00000000

PLL D(5:0) – Six least significant bits of a 14-bit unsigned integer valid values for D are from

zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be

written into these registers that would result in a D value outside the valid range.

D1-D0

Reserved. Do not write to these bits.

Page 0 / Register 7:

DAC Datapath Setup Register

BIT

READ/

RESET

DESCRIPTION

WRITE

VALUE

R/W

Fsref setting

0: Fsref = 48-kHz

1: Fsref = 44.1-kHz

R/W

Reserved. Only write zero to this bit.

R/W

DAC Dual Rate Control 0: DAC dual rate mode is disabled 1: DAC dual rate mode is enabled

D4–D3

R/W

Left DAC Datapath Control

00: Left DAC datapath is off (muted)

01: Left DAC datapath plays left channel input data

10: Left DAC datapath plays right channel input data

11: Left DAC datapath plays mono mix of left and right channel input data

D2–D1

R/W

Right DAC Datapath Control

00: Right DAC datapath is off (muted)

01: Right DAC datapath plays right channel input data

10: Right DAC datapath plays left channel input data

11: Right DAC datapath plays mono mix of left and right channel input data

R/W

Reserved. Only write zero to this register.

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