TLV320DAC32 datasheet(21/70 Pages) TI1

21 / 70 page

2C CONTROL MODE

SDA

SCL

HD-STA

0.9

SU-STO

0.9

SU-STA

0.9

HD-STA

0.9

T0114-02

TLV320DAC32

www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008

change in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now

access registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence

“0x00” to register 0, the page control register, to change the active page back to page 0. After a recommended

read of the page control register, all further read/write operations to addresses 1 to 127 will now access page 0

registers again.

It is considered to be a best practice, that when writing to PAGE 1, all five of the digital filter’s coefficients of the

Bi-Quad structure be updated to the new values before resuming digital audio playback.

The TLV320DAC32 supports the I2C control protocol using 7-bit addressing and is capable of both standard and

fast modes. For I2C fast mode, note that the minimum timing for each of tHD-STA, tSU-STA, and tSU-STO is 0.9 µs, as

seen in Figure 23. The TLV320DAC32 will respond to the I2C address of 0011000. I2C is a two-wire open-drain

interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus

lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled

HIGH by pull-up resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two

devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Figure 23. I2C Interface Timing

Communication on the I2C bus always takes place between two devices, one acting as the master and the other

acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of

the master. Some I2C devices can act as masters or slaves, but the TLV320DAC32 can only act as a slave

device.

An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted

across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate

level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA

line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the

receiver’s shift register.

The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads

from a slave, the slave drives the data line; when a master sends info to a slave, the master drives the data line.

The master always drives the clock line. The TLV320DAC32 never drives SCL, because it cannot act as a

master. On the TLV320DAC32, SCL is an input only.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When

communication is taking place, the bus is active. Only master devices can start a communication. They do this by

causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock

line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its

counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from

HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC32

TLV320DAC32 bảng dữ liệu(PDF) 21 Page - Texas Instruments

TLV320DAC32 bảng dữ liệu(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL