TLK1201ARCP_16 datasheet(12/24 Pages) TI1

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TRANSMITTER/RECEIVER CHARACTERISTICS

80%

50%

20%

80%

50%

20%

∼ V

80%

20%

0 V

∼ 1V

∼ −1V

TX+

TX−

VOD

TLK1201ARCP, TLK1201AIRCP

ETHERNET TRANSCEIVERS

SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT(1)

Rt = 50Ω

600

850

1100

VOD = |TxD-TxN|

Rt = 75 Ω

800

1050

1200

Rt = 50Ω

V(cm)

Transmit common mode voltage range

1100

1250

1400

Rt = 75 Ω

Receiver input voltage requirement,

200

1600

VID = |RxP - RxN|

Receiver common mode voltage range, (RxP

1000

1250

2250

+ RxN)/2

Ilkg(R)

Receiver input leakage current

-350

350

μA

Receiver input capacitance

Differential output jitter, Random +

deterministic, PRBS pattern,

0.24

Rω = 125 MHz

t(TJ)

Serial data total jitter (peak-to-peak)

Differential output jitter, Random +

deterministic, PRBS pattern,

0.2

Rω = 106.25 MHz

Differential output jitter, PRBS pattern,

t(DJ)

Serial data deterministic jitter (peak-to-peak)

0.10

Rω = 125 MHz

tr, tf

Differential signal rise, fall time (20% to 80%)

RL = 50 Ω, CL = 5 pF, See Figure 7

100

250

Differential input jitter, Random +

0.25

deterministic, Rω = 125 MHz

Serial data jitter tolerance minimum required

Differential input jitter, random +

eye opening, (per IEEE-802.3 specification)

determinisitc, PRBS pattern at zero

0.3

crossing

Receiver data acquisition lock time from

500

μs

powerup

Data relock time from loss of synchronization

1024

Bit times

TBI modes

See Figure 1

td(Txlatency)

Tx latency

DDR mode

TBI modes

See Figure 6

DDR mode

TBI mode

600–620 Mbps

td(Rxlatency)

Rx latency

DDR mode

600–620 Mbps

TBI mode

1228.8 Mbps

DDR mode

1228.8 Mbps

(1)

UI = serial bit time

Figure 7. Differential and Common-Mode Output Voltage Definitions

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