34AA04T-ESLASHST datasheet(16/36 Pages) MICROCHIP

16 / 36 page

34AA04

DS20005271B-page 16

 2014 Microchip Technology Inc.

FIGURE 9-1:

SET WRITE PROTECTION

TABLE 9-3:

DEVICE RESPONSE WHEN DEFINING WRITE PROTECTION

9.2

Clear All Write Protection (CWP)

The Clear All Write Protection (CWP) command resets

all of the write protection in a single operation. It is

executed in the same manner as a SWP command,

except using the CWP control byte (Table 9-2).

The 34AA04 will always acknowledge and execute a

CWP command if an internal write cycle is not in

progress, regardless of the state of write protection.

9.3

Read Protection Status (RPS)

The Read Protection Status (RPS) commands provide

a way of determining whether or not the specified

block is currently write-protected.

Following the Start condition, the master transmits the

control byte for the desired RPS command (Table 9-2),

with the R/W bit set to logic ‘1’. If the specified block is

not write-protected, the 34AA04 will respond with an

Acknowledge signal. If the block is currently write-

protected, an Acknowledge will not be generated.

Regardless of the result, the master must read at least

one dummy byte from the 34AA04, transmitting a Not

Acknowledge signal after each byte, and generate a

Stop condition to end the command (Figure 9-3).

FIGURE 9-2:

CLEAR ALL WRITE PROTECTION

Status

Command

ACK

Address

ACK

Data Byte

ACK

Write Cycle

Protected with SWPn

SWPn

NoACK

Don’t Care

NoACK

Don’t Care

NoACK

CWP

ACK

Don’t Care

ACK

Don’t Care

ACK

Yes

Not Protected

SWPn or CWP

ACK

Don’t Care

ACK

Don’t Care

ACK

Yes

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Dummy

Byte

1 0

Note 1:

Chip Select bits A0-A2 vary depending on which SWP command is being executed.

Dummy

Byte

The 34AA04 will only acknowledge if the specified block is not currently write-protected.

A0 Pin

VHV

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Dummy

Byte

1 0

Dummy

Byte

011

A0 Pin

VHV

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