34AA04T-ESLASHST datasheet(7/36 Pages) MICROCHIP

7 / 36 page

 2014 Microchip Technology Inc.

DS20005271B-page 7

34AA04

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 4-2:

BUS TIMEOUT

4.7

Device Addressing

A control byte is the first byte received following the

Start condition from the master device. The first part of

the control byte consists of a 4-bit control code which is

set to ‘1010’ for normal read and write operations and

‘0110’ for accessing the software write-protect features

and bank selection. The control byte is followed by

three Chip Select bits (A2, A1, A0). The Chip Select bits

allow the use of up to eight 34AA04 devices on the

same bus and are used to determine which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond.

The eighth bit of slave address determines if the master

device wants to read or write to the 34AA04

(Figure 4-3). When set to a one, a read operation is

selected. When set to a zero, a write operation is

selected.

FIGURE 4-3:

CONTROL BYTE

ALLOCATION

SCL

SDA

(A)

(B)

(D)

(A)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL

TTIMEOUT(MIN)TTIMEOUT(MAX)

TLOW < TTIMEOUT(MIN): Bus interface does not reset.

TTIMEOUT(MIN) < TLOW < TTIMEOUT(MAX): Bus interface may or may not reset.

TTIMEOUT(MAX) < TLOW: Bus interface will reset.

Operation

Control

Code

Chip

Select

R/W

Read

1010

A2 A1 A0

Write

1010

A2 A1 A0

Read Write-Protect/

Bank Address

0110

A2 A1 A0

Set Write-Protect/

Bank Address

0110

A2 A1 A0

Start

Read/Write

Slave Address

R/W A

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