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34AA04T-E/ST bảng dữ liệu(PDF) 8 Page - Microchip Technology

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34AA04T-E/ST bảng dữ liệu(HTML) 8 Page - Microchip Technology

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34AA04
DS20005271B-page 8
 2014 Microchip Technology Inc.
5.0
BANK ADDRESSING
To support backwards-compatibility with DDR2/3
(JEDEC EE1002) SPD EEPROMs, the memory array
of the 34AA04 is divided into two separate 256-byte
banks. The Set Bank Address (SBA) commands are
used to set the bank address to either 0 or 1. The
Read Bank Address (RBA) command is used to
determine which bank is currently selected.
TABLE 5-1:
BANK ADDRESS RANGE
TABLE 5-2:
BANK ADDRESSING INSTRUCTION SET
5.1
Set Bank Address (SBA)
The Set Bank Address (SBA) commands are used to
select the array bank for future read and write
operations.
The master generates a Start condition followed by the
corresponding control byte for the chosen SBA
command (Table 5-2), with the R/W bit set to a logic
‘0’. Note that Chip Select bit A0 of the control byte
effectively determines which bank is selected. The
34AA04 will respond with an Acknowledge, and then
the master transmits two dummy bytes. The 34AA04
will not acknowledge either dummy byte. Finally, the
master generates a Stop condition to end the
operation (Figure 5-1).
Array Read and Write commands will operate in the
newly-selected bank until another SBA command is
executed, or the 34AA04 experiences a POR or BOR
event.
FIGURE 5-1:
SET BANK ADDRESS
Note 1:
The bank address is volatile and is reset
to Bank 0 upon power-up.
2:
The comparison between the A0, A1, and
A2 pins and the corresponding Chip
Select bits is disabled for Bank Select
commands.
Note:
Sequential read operations cannot
cross a bank boundary and will roll over
back to the beginning of the selected
bank.
Bank
Logical Array Address
Bank 0
000h-0FFh
Bank 1
100h-1FFh
Function
Abbr
Control Byte
A0 Pin
Control Code
Chip Select Bits
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Set Bank Address to 0
SBA0
0110
1100
0
, 1, or VHV
Set Bank Address to 1
SBA1
1110
0
, 1, or VHV
Read Bank Address
RBA
1101
0
, 1, or VHV
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Dummy
Byte
A
C
K
01
1 0
0
Dummy
Byte
11
A
1
0
N
o
A
C
K
N
o
A
C
K
Note 1:
Chip Select bit A0 specifies which bank to select.



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