SN65DP149 datasheet(9/54 Pages) TI1

9 / 54 page

SN65DP149, SN75DP149

www.ti.com

SLLSEL2C – SEPTEMBER 2015 – REVISED JULY 2016

Product Folder Links: SN65DP149 SN75DP149

Submit Documentation Feedback

7.6 Differential Input Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DR_RX_DATA

Ddata lanes data rate

0.25

3.4

Gbps

DR_RX_CLK

Clock lanes clock rate

340

MHz

tRX_DUTY

Input clock duty circle

40%

50%

60%

tCLK_JIT

Input clock jitter tolerance

0.3

Tbit

tDATA_JIT

Input data jitter tolerance

Test the TTP2, see Figure 7

150

TRX_INTRA

Input intra-pair skew tolerance

Test at TTP2 when DR = 1.6-Gbps, see

Figure 7

112

TRX_INTER

Input inter-pair skew tolerance

1.8

EQH(D)

Fixed EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = H; Fixed EQ gain,

test at 3.4-Gbps

EQL(D)

Fixed EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = L; Fixed EQ gain,

test at 3.4-Gbps

7.5

EQZ(D)

Adaptive EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = Z; adaptive EQ

EQ(c)

EQ gain for clock lane IN_CLKn/p

EQ_SEL/A0 = H,L,NC

RINT

Input differential termination impedance

100

120

Ω

VITERM

Input termination voltage

OE = H

0.7

VID_PP

Input differential voltage (peak to peak)

Tested at TTP2, check Figure 7

1200

mVPP

SN65DP149 bảng dữ liệu(PDF) 9 Page - Texas Instruments

SN65DP149 bảng dữ liệu(HTML) 9 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

bảng dữ liệu tải về

Link URL