LM317SSLASHNOPB datasheet(27/48 Pages) TI1

27 / 48 page

LM117, LM317-N

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SNVS774P – MAY 2004 – REVISED OCTOBER 2015

10 Power Supply Recommendations

The input supply to the LM117 and LM317-N must be kept at a voltage level such that its maximum input to

output differential voltage is not exceeded. The minimum dropout voltage must also be met with extra headroom

when possible to keep the LM117 and LM317-N in regulation. An input capacitor is recommended, especially

when the input pin is located more than 6 inches away from the power supply source. For more information

regarding capacitor selection, refer to External Capacitors.

11 Layout

11.1 Layout Guidelines

Some layout guidelines must be followed to ensure proper regulation of the output voltage with minimum noise.

Traces carrying the load current must be wide to reduce the amount of parasitic trace inductance and the

feedback loop from VOUT to ADJ must be kept as short as possible. To improve PSRR, a bypass capacitor can

be placed at the ADJ pin and must be located as close as possible to the IC. In cases when VIN shorts to ground,

an external diode must be placed from VOUT to VIN to divert the surge current from the output capacitor and

protect the IC. Similarly, in cases when a large bypass capacitor is placed at the ADJ pin and VOUT shorts to

ground, an external diode must be placed from ADJ to VOUT to provide a path for the bypass capacitor to

discharge. These diodes must be placed close to the corresponding IC pins to increase their effectiveness.

11.2 Layout Example

Figure 36. Layout Example (SOT-223)

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