DP83950B datasheet(64/80 Pages) NSC

64 / 80 page

80 RIC Registers (Continued)

Interrupt and Management Configuration Register (Page 0H Address 16H)

This register powers up with all bits set to one and must be initialized by a processor write cycle before any events will generate

interrupts

IFC

IHC

ILC

IFF

IREC

ICOL

IPART

MIFCON

Bit

Symbol

Description

MIFCON

MANAGEMENT INTERFACE CONFIGURATION

0 All Packets repeated are transmitted over the Management bus

1 Packets repeated by the RIC which do not have a Start of Frame Delimiters are not transmitted

over the Management bus

IPART

INTERRUPT ON PARTITION

0 Interrupts will be generated(1) if a port becomes Partitioned

1 No interrupts are generated by this condition

ICOL

INTERRUPT ON COLLISION

0 Interrupts will be generated(1) if this RIC has a port which experiences a collision Single RIC

applications or contains a port which experiences a receive collision or is the first port to suffer a

transmit collision in a packet in Multi-RIC applications

1 No interrupts are generated by this condition

IREC

INTERRUPT ON RECEIVE

0 Interrupts will be generated(1) if this RIC contains the receive port for packet or collision activity

1 No interrupts are generated by this condition

IFF

INTERRUPT ON FLAG FOUND

0 Interrupts will be generated(2) if one or more than one of the flags in the flag array is true

1 No interrupts are generated by this condition

ILC

INTERRUPT ON LOW COUNT

0 Interrupt generated(2) when one or more of the Event Counters holds a value less than 256

counts

1 No effect

IHC

INTERRUPT ON HIGH COUNT

0 Interrupt generated(2) when one or more of the Event Counters holds a value in excess of 49152

counts

1 No effect

IFC

INTERRUPT ON FULL COUNTER

0 Interrupt generated(2) when one or more of the Event Counters is full

1 No effect

Note 1

(RTI pin goes active)

Note 2

(ELI pin goes active)

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