DP83950B datasheet(60/80 Pages) NSC

60 / 80 page

80 RIC Registers (Continued)

Real Time Interrupt Register (Address 0FH)

The Real Time Interrupt register (RTI) contains information which may change on a packet by packet basis Any remaining

interrupts which have not been serviced before the following packet is transmitted are cleared Since multiple interrupt sources

may be displayed by the RTI a priority scheme is implemented A read cycle to the RTI gives the interrupt source and an address

vector indicating the RIC port which generated the interrupt The order of priority for the display of interrupt information is as

follows

1 The receive source of network activity (Port N)

2 The first RIC port showing collision

3 A port partitioned or reconnected

During the repetition of a single packet it is possible that multiple ports may be partitioned or alternatively reconnected The

ports have equal priority in displaying partitionreconnection information This data is derived from the ports by the RTI register

as it polls consecutively around the ports

Reading the RTI clears the particular interrupt If no interrupt sources are active the RTI returns a no valid interrupt status

IVCTR3

IVCTR2

IVCTR1

IVCTR0

ISRC3

ISRC2

ISRC1

ISRC0

Bit

Symbol

Description

Access

D(30)

ISCR(30)

INTERRUPT SOURCE

These four bits indicate the reason why the interrupt was generated

D(74)

IVCTR(30)

INTERRUPT VECTOR

This field defines the port address responsible for generating the

interrupt

The following table shows the mapping of interrupt sources onto the D3 to D0 pins Essentially each of the three interrupt

sources has a dedicated bit in this field If a read to the RTI produces a low logic level on one of these bits then the interrupt

source may be directly decoded Associated with the source of the interrupt is the port where the event is occurring If no

unmasked events (receive collision etc) have occurred when the RTI is read then an all ones pattern is driven by the RIC onto

the data pins

Comments

PA3

PA2

PA1

PA0

First Collision

PA(30) e Collision Port Address

PA3

PA2

PA1

PA0

Receive

PA(30) e Receive Port Address

PA3

PA2

PA1

PA0

Partition Reconnection

PA(30) e Partition Port Address

No Valid Interrupt

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