V62SLASH12615-01XE-R datasheet(81/92 Pages) TI1

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DP83848-EP

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SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

Table 9-20. PHY Control Register (PHYCR), Address 0x19 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

Pause Transmit Negotiated:

Indicates that pause transmit should be enabled in the MAC. Based on

ANAR[11:10] and ANLPAR[11:10] settings.

PAUSE_TX

0, RO

This function shall be enabled according to IEEE 802.3 Annex 28B

Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest

Common Denominator is a full duplex technology.

BIST Force Error:

1 = Force BIST Error

BIST_FE

0, RW/SC

0 = Normal operation

This bit forces a single error, and is self clearing

BIST Sequence select:

PSR_15

0, RW

1 = PSR15 selected

0 = PSR9 selected

BIST Test Status:

1 = BIST pass

BIST_STATUS

0, LL/RO

0 = BIST fail. Latched, cleared when BIST is stopped

For a count number of BIST errors, see the BIST Error Count in the

CDCTRL1 register.

BIST Start:

BIST_START

0, RW

1 = BIST start

0 = BIST stop

Bypass LED Stretching:

This will bypass the LED stretching and the LEDs will reflect the internal

value.

BP_STRETCH

0, RW

1 = Bypass LED stretching

0 = Normal operation

LED_CNFG[1]

0, RW

LEDs Configuration:

LED_CNFG

LED_

Mode

LED_CNFG[0]

Strap, RW

[1]

CNFG[0]

Description

Don’t care

Mode 1

Mode 2

Mode 3

In Mode 1, LEDs are configured as follows:

LED_LINK = ON for Good Link, OFF for No Link

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/COL = ON for Activity, OFF for No Activity

In Mode 2, LEDs are configured as follows:

LED_LINK = ON for good Link, BLINK for Activity

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/COL = ON for Collision, OFF for No Collision

Full Duplex, OFF for Half Duplex

In Mode 3, LEDs are configured as follows:

LED_LINK = ON for Good Link, BLINK for Activity

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/COL = ON for Full Duplex, OFF for Half Duplex

4:0

PHYADDR[4:0]

Strap, RW

PHY Address: PHY address for port

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