V62SLASH12615-01XE-R datasheet(58/92 Pages) TI1

58 / 92 page

RJ45

RD–

RD+

TD–

TD+

RD-

RD+

TD-

TD+

1:1

0.1μF*

1:1

49.9

Ω

49.9Ω

0.1μF*

Vdd

NOTE: Center tap is pulled to V

DD.

0.1µF

All values are typical and are +/- 1%

Vdd

49.9

Ω

49.9Ω

0.1µF

Vdd

*Place capacitors close to the

transformer center taps.

Place resistors and

capacitors close to

the device.

Common mode chokes

may be required.

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

www.ti.com

DESIGN GUIDELINES

7.1

TPI Network Circuit

Figure 7-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial

list of recommended transformers. It is important that the user realize that variations with PCB and

component characteristics requires that the application be tested to ensure that the circuit meets the

requirements of the intended application.

Figure 7-1. 10/100 Mb/s Twisted Pair Interface

7.2

ESD Protection

Typically, ESD precautions are predominantly in effect when handling the devices or board before being

installed in a system. In those cases, strict handling procedures need be implemented during the

manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is

assembled, internal components are less sensitive from ESD events.

See for ESD rating.

7.3

Clock In (X1) Requirements

The DP83848 supports an external CMOS level oscillator source or a crystal resonator device.

7.3.1

Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 7-1

and Table 7-2.

DESIGN GUIDELINES

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Product Folder Links: DP83848-EP

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