V62SLASH12615-01XE-R datasheet(78/92 Pages) TI1

78 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

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9.3.4

False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU

managed object class of Clause 30 of the IEEE 802.3u specification.

Table 9-15. False Carrier Sense Counter Register (FCSCR), Address 0x14

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

False Carrier Event Counter:

7:0

FCSCNT[7:0]

0, RO/COR

This 8-bit counter increments on every false carrier event. This

counter sticks when it reaches its max count (FFh).

9.3.5

Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within

the PHY managed object class of Clause 30 of the IEEE 802.3u specification.

Table 9-16. Receiver Error Counter Register (RECR), Address 0x15

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

RX_ER Counter:

When a valid carrier is present and there is at least one occurrence of

an invalid data symbol, this 8-bit counter increments for each receive

7:0

RXERCNT[7:0]

0, RO/COR

error detected. This event can increment only once per valid carrier

event. If a collision is present, the attribute will not increment. The

counter sticks when it reaches its max count.

9.3.6

100 Mb/s PCS Configuration and Status Register (PCSR)

This register contains event status and enables for the interrupt function. If an event has occurred since

the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the

set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

Table 9-17. 100 Mb/s PCS Configuration and Status Register (PCSR), Address 0x16

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

RESERVED

<00>, RO

RESERVED: Writes ignored, Read as 0

RESERVED

RESERVED: Must be zero

RESERVED

RESERVED: Must be zero

100Mbs True Quiet Mode Enable:

TQ_EN

0, RW

1 = Transmit True Quiet Mode

0 = Normal Transmit Mode

Signal Detect Force PMA:

SD FORCE PMA

0, RW

1 = Forces Signal Detection in PMA

0 = Normal SD operation

Signal Detect Option:

SD_OPTION

1, RW

1 = Enhanced signal detect algorithm

0 = Reduced signal detect algorithm

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