V62SLASH12615-01XE-R datasheet(45/92 Pages) TI1

45 / 92 page

DP83848-EP

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SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

5.1.3

Carrier Sense

Carrier sense (CRS) is asserted due to receive activity, once valid data is detected via the squelch

function during 10 Mb/s operation. During 100 Mb/s operation CRS is asserted when a valid link (SD) and

two non-contiguous zeros are detected on the line.

For 10 or 100 Mb/s half duplex operation, CRS is asserted during either packet transmission or reception.

For 10 or 100 Mb/s full duplex operation, CRS is asserted only due to receive activity.

CRS is deasserted following an end of packet.

5.2

Reduced MII Interface

The DP83848 incorporates the reduced media independent interface (RMII) as specified in the RMII

specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a

MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a

time using the 50 MHz RMII_REF clock for both transmit and receive. The following pins are used in RMII

mode:

•

TX_EN

•

TXD[1:0]

•

RX_ER (optional for Mac)

•

CRS_DV

•

RXD[1:0]

•

X1 (RMII Reference clock is 50 MHz)

In addition, the RMII mode supplies an RX_DV signal which allows for a simpler method of recovering

receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for

systems which do not require CRS, such as systems that only support fullduplex operation. This signal is

also useful for diagnostic testing where it may be desirable to loop Receive RMII data directly to the

transmitter.

Since the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is

sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached

device can sample the data every 10 clocks.

RMII mode requires a 50 MHz oscillator be connected to the device X1 pin. A 50 MHz crystal is not

supported.

To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive

clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is

programmable to minimize propagation delay based on expected packet size and clock accuracy. This

allows for supporting a range of packet sizes including jumbo frames.

The elasticity buffer will force frame check sequence errors for packets which overrun or underrun the

FIFO. Underrun and Overrun conditions can be reported in the RMII and bypass register (RBR). The

following table indicates how to program the elasticity buffer fifo (in 4-bit increments) based on expected

max packet size and clock accuracy. It assumes both clocks (RMII reference clock and far-end transmitter

clock) have the same accuracy.

Table 5-1. Supported Packet Sizes at ±50ppm and ±100ppm for Each Clock

START THRESHOLD

RECOMMENDED PACKET SIZE

LATENCY TOLERANCE

RBR[1:0]

at ±50ppm

at ±100ppm

1 (4-bits)

2 bits

2400 bytes

1200 bytes

2 (8-bits)

6 bits

7200 bytes

3600 bytes

3 (12-bits)

10 bits

12000 bytes

6000 bytes

0 (16-bits)

14 bits

16800 bytes

8400 bytes

FUNCTIONAL DESCRIPTION

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