CS5530 datasheet(49/241 Pages) NSC

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Funcitonal Description (Continued)

3.3

RESETS AND CLOCKS

The operations of resets and clocks in the CS5530 are

described in this section of the Functional Description.

3.3.1

Resets

The CS5530 generates two reset signals, PCI_RST# to

the PCI bus and CPU_RST to the GXLV processor. These

resets are generated after approximately 100 µs delay

from POR# active as depicted in Figure 3-5.

At any state, Power-on/Resume/Reset, the 14.31818 MHz

oscillator must be active for the resets to function.

3.3.2

ISA Clock

The CS5530 creates the ISACLK from dividing the PCI-

CLK. For ISA compatibility, the ISACLK nominally runs at

8.33 MHz or less. The ISACLK dividers are programmed

via F0 Index 50h[2:0] as shown in Table 3-8.

Figure 3-5. CS5530 Reset

Table 3-8. ISACLK Divider Bits

Bit

Description

F0 Index 50h

PIT Control/ISA CLK Divider (R/W)

Reset Value = 7Bh

2:0

ISA Clock Divisor: Determines the divisor of the PCI clock used to make the ISA clock, which is typically

programmed for approximately 8 MHz:

000 = Divide by one

100 = Divide by five

001 = Divide by two

101 = Divide by six

010 = Divide by three

110 = Divide by seven

011 = Divide by four

111 = Divide by eight

If PCI clock = 25 MHz, use setting of 010 (divide by 3). If PCI clock = 30 or 33 MHz, use a setting of 011 (divide by 4).

POR#

CPU_RST

PCI_RST#

100 µs

POR# minimum pulse width for CS5530 only (i.e., not a system specification) = 100 µs and 14 MHz must be running.

9ms

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