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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MB9B360R bảng dữ liệu(PDF) 138 Page - Cypress Semiconductor |
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MB9B360R bảng dữ liệu(HTML) 138 Page - Cypress Semiconductor |
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138 / 166 page  Document Number: 002-04872 Rev.*A Page 138 of 166 MB9B360R Series High-Speed Mode Clock CLK (All values are referred to V IH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin name Conditions Value Remarks Min Max Clock frequency Data Transfer Mode fPP S_CLK CCARD ≤ 10pF (1card) 0 32 MHz Clock low time tWL S_CLK 7 - ns Clock high time tWH S_CLK 7 - ns Clock rising time tTLH S_CLK - 3 ns Clock falling time tTHL S_CLK - 3 ns Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin name Conditions Value Remarks Min Max Input set-up time tISU S_CMD, S_DATA3:0 CCARD ≤ 10pF (1card) 8 - ns Input hold time tIH S_CMD, S_DATA3:0 2 - ns Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin name Conditions Value Remarks Min Max Output Delay time during Data Transfer Mode tODLY S_CMD, S_DATA3:0 CL ≤ 40pF (1card) - 22 ns Output Hold time tOH S_CMD, S_DATA3:0 CL ≥ 15pF (1card) 2.5 - ns Total System capacitance for each line* CL - 1card - 40 pF *: In order to satisfy severe timing, host shall drive only one card. High-Speed Mode Notes: • The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. • In high-speed mode, set the Clock frequency (fPP) and the AHB Bus Clock frequency to the same values. VIL VIL tWL tWH VIH VIH VIH tTHL tTLH tISU VIH VIL VIH VIL tIH VOH VOL VOH VOL tODLY(Max) tOH(Min) 50%VCC 50%VCC S_CLK (SD Clock) S_CMD, S_DATA3:0 (Card Input) S_CMD, S_DATA3:0 (Card Output) |
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