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TDA9885TS/V3 bảng dữ liệu(PDF) 20 Page - NXP Semiconductors

tên linh kiện TDA9885TS/V3
Giải thích chi tiết về linh kiện  I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
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nhà sản xuất  PHILIPS [NXP Semiconductors]
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TDA9885TS/V3 bảng dữ liệu(HTML) 20 Page - NXP Semiconductors

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2003 Oct 02
20
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard
alignment-free IF-PLL demodulators
TDA9885; TDA9886
9.2.4
DATA BYTE FOR DATA MODE
Table 14 Bit description of SAD register for data mode (SAD = 10)
Note
1. For positive modulation choose 6.5 MHz.
Table 15 Options in extended TV mode; bit B3 = 0 of SAD 00 register
Note
1. The corresponding port function has to be disabled (set to ‘high-impedance’); see Table 11 and Chapter 12, Table
of Characteristics, note 12.
BIT
VALUE
DESCRIPTION
E7
VIF-AGC and port features
dependent on bit E5; see Table 15
E6
L standard PLL gating
1
gating in case of 36 % positive modulation
0
gating in case of 0 % positive modulation
E5
VIF, SIF and tuner minimum gain
dependent on bit E7; see Table 15
E4 to E2
Vision intermediate frequency selection
see Table 16
E1 and E0
Sound intercarrier frequency selection (sound 2nd IF)
00
fFM = 4.5 MHz
01
fFM = 5.5 MHz
10
fFM = 6.0 MHz
11
fFM = 6.5 MHz; note 1
FUNCTION
BIT E7 = 0
BIT E7 = 1
BIT E5 = 0
BIT E5 = 1
BIT E5 = 0
BIT E5 = 1
Pin OP1
port function
port function
port function
VIF-AGC external input(1)
Pin OP2
port function
port function
VIF-AGC output(1)
port function
Gain
normal gain
minimum gain
normal gain
external gain



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