TDA9885TSSLASHV3 datasheet(10/56 Pages) PHILIPS

10 / 56 page

2003 Oct 02

Philips Semiconductors

Product speciﬁcation

I2C-bus controlled single and multistandard

alignment-free IF-PLL demodulators

TDA9885; TDA9886

FUNCTIONAL DESCRIPTION

Figure 1 shows the simplified block diagram of the device

which comprises the following functional blocks:

• VIF amplifier

• Tuner AGC and VIF-AGC

• VIF-AGC detector

• Frequency Phase-Locked Loop (FPLL) detector

• VCO and divider

• AFC and digital acquisition help

• Video demodulator and amplifier

• Sound carrier trap

• SIF amplifier

• SIF-AGC detector

• Single reference QSS mixer

• AM demodulator

• FM demodulator and acquisition help

• Audio amplifier and mute time constant

• Internal voltage stabilizer

• I2C-bus transceiver and MAD (module address).

8.1

VIF ampliﬁer

The VIF amplifier consists of three AC-coupled differential

stages. Gain control is performed by emitter degeneration.

The total gain control range is typically 66 dB. The

differential input impedance is typically 2 k

Ω in parallel with

3 pF.

8.2

Tuner AGC and VIF-AGC

This block adapts the voltages, generated at the VIF-AGC

and SIF-AGC detectors, to the internal signal processing

at the VIF and SIF amplifiers and performs the tuner AGC

control current generation. The onset of the tuner AGC

control current generation can be set either via the I2C-bus

(see Table 13) or optionally by a potentiometer at pin TOP

(in case that the I2C-bus information cannot be stored,

related to the device). The presence of a potentiometer is

automatically detected and the I2C-bus setting is disabled.

Furthermore, derived from the AGC detector voltage, a

comparator is used to test if the corresponding VIF input

voltage is higher than 200

µV. This information can be

read out via the I2C-bus (bit VIFLEV = 1).

8.3

VIF-AGC detector

Gain control is performed by sync level detection (negative

modulation) or peak white detection (positive modulation).

For negative modulation, the sync level voltage is stored at

an integrated capacitor by means of a fast peak detector.

This voltage is compared with a reference voltage

(nominal sync level) by a comparator which charges or

discharges the integrated AGC capacitor for the

generation of the required VIF gain. The time constants for

decreasing or increasing the gain are nearly equal and the

total AGC reaction time is fast to cope with ‘aeroplane

fluttering’.

For positive modulation, the white peak level voltage is

compared with a reference voltage (nominal white level)

by a comparator which charges (fast) or discharges (slow)

the external AGC capacitor directly for the generation of

the required VIF gain. The need of a very long time

constant for VIF gain increase is because the peak white

level may appear only once in a field. In order to reduce

this time constant, an additional level detector increases

the discharging current of the AGC capacitor (fast mode)

in the event of a decreasing VIF amplitude step controlled

by the detected actual black level voltage. The threshold

level for fast mode AGC is typically

−6 dB video amplitude.

The fast mode state is also transferred to the SIF-AGC

detector for speed-up. In case of missing peak white

pulses, the VIF gain increase is limited to typically +3 dB

by comparing the detected actual black level voltage with

a corresponding reference voltage.

8.4

FPLL detector

The VIF amplifier output signal is fed into a frequency

detector and into a phase detector via a limiting amplifier

for removing the video AM.

During acquisition the frequency detector produces a

current proportional to the frequency difference between

the VIF and the VCO signals. After frequency lock-in the

phase detector produces a current proportional to the

phase difference between the VIF and the VCO signals.

The currents from the frequency and phase detectors are

charged into the loop filter which controls the VIF VCO and

locks it to the frequency and phase of the VIF carrier.

For a positive modulated VIF signal, the charging currents

are gated by the composite sync in order to avoid signal

distortion in case of overmodulation. The gating depth is

switchable via the I2C-bus.

TDA9885TS/V3 bảng dữ liệu(PDF) 10 Page - NXP Semiconductors

TDA9885TS/V3 bảng dữ liệu(HTML) 10 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL