DSP56362AD datasheet(19/168 Pages) MOTOROLA

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Signal/Connection Descriptions

Interrupt and Mode Control

MOTOROLA

DSP56362 Advance Information

1-11

MODC/IRQC

Input

Mode Select C/External Interrupt Request C—

MODC/IRQC is an active-low Schmitt-trigger input,

internally synchronized to the DSP clock. MODC/IRQC

selects the initial chip operating mode during hardware

reset and becomes a level-sensitive or negative-edge-

triggered, maskable interrupt request input during

normal instruction processing. MODA, MODB, MODC,

and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is

deasserted. If IRQC is asserted synchronous to

CLKOUT, multiple processors can be resynchronized

using the WAIT instruction and asserting IRQC to exit

the wait state.

This input is 5 V tolerant.

MODD/IRQD

Input

Mode Select D/External Interrupt Request D—

MODD/IRQD is an active-low Schmitt-trigger input,

internally synchronized to the DSP clock. MODD/IRQD

selects the initial chip operating mode during hardware

reset and becomes a level-sensitive or negative-edge-

triggered, maskable interrupt request input during

normal instruction processing. MODA, MODB, MODC,

and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is

deasserted. If IRQD is asserted synchronous to

CLKOUT, multiple processors can be resynchronized

using the WAIT instruction and asserting IRQD to exit

the wait state.

This input is 5 V tolerant.

Table 1-8 Interrupt and Mode Control (Continued)

Signal Name

Type

State during

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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