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DSP56362AD bảng dữ liệu(PDF) 91 Page - Motorola, Inc

tên linh kiện DSP56362AD
Giải thích chi tiết về linh kiện  24-Bit Audio Digital Signal Processor
PDF  168 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
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DSP56362AD bảng dữ liệu(HTML) 91 Page - Motorola, Inc

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Specifications
Parallel Host Interface (HDI08) Timing
MOTOROLA
DSP56362 Advance Information
2-53
342
Delay from DMA HACK deassertion to HOREQ
assertion
• For “Last Data Register” read5
ns
2
× TC + 19.1 39.1 —
• For “Last Data Register” write5
1.5
× TC + 19.1 34.1 —
• For other cases
0.0
—
343
Delay from DMA HACK assertion to HOREQ
deassertion
•HROD = 05
——
20.2
ns
344
Delay from DMA HACK assertion to HOREQ
deassertion for “Last Data Register” read or
write
• HROD = 1, open drain Host Request5, 11
——
300.
0
ns
Notes:
1.
See Host Port Usage Considerations in the DSP56362 User Design Manual.
2.
In the timing diagrams below, the controls pins are drawn as active low. The pin
polarity is programmable.
3.
VCC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF
4.
The read data strobe is HRD in the dual data strobe mode and HDS in the single
data strobe mode.
5.
The “last data register” is the register at address $7, which is the last location to be
read or written in data transfers. This is RXL/TXL in the little endian mode (HBE = 0),
or RXH/TXH in the big endian mode (HBE = 1).
6.
This timing is applicable only if a read from the “last data register” is followed by a
read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits,
or waiting for the assertion of the HOREQ signal.
7.
This timing is applicable only if two consecutive reads from one of these registers
are executed.
8.
The write data strobe is HWR in the dual data strobe mode and HDS in the single
data strobe mode.
9.
The data strobe is host read (HRD) or host write (HWR) in the dual data strobe
mode and host data strobe (HDS) in the single data strobe mode.
10. The host request is HOREQ in the single host request mode and HRRQ and HTRQ
in the double host request mode.
11. In this calculation, the host request signal is pulled up by a 4.7 k
Ω resistor in the
open-drain mode.
Table 2-20 Host Interface (HDI08) Timing1, 2 (Continued)
No.
Characteristics3
Expression
100 MHz
Unit
Min Max
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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