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LP5952TLX-0.7/NOPB bảng dữ liệu(PDF) 21 Page - Texas Instruments

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LP5952TLX-0.7/NOPB bảng dữ liệu(HTML) 21 Page - Texas Instruments

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VOUT
LM5050-1
Gate
IN
OUT
OFF
VS
GND
VIN
R1
GND
D1
D4
CIN
LM5050-1, LM5050-1-Q1
www.ti.com
SNVS629E – MAY 2011 – REVISED DECEMBER 2015
9 Power Supply Recommendations
When the LM5050-1/-Q1 shuts off the external MOSFET, transient voltages will appear on the input and output
due to reverse recovery, as discussed in Short Circuit Failure of an Input Supply.To prevent LM5050-1 and
surrounding components from damage under the conditions of a direct input short circuit, it is necessary to clamp
the negative transient at IN, and OUT pins with TVS.
10 Layout
10.1 Layout Guidelines
The typical PCB layout for LM5050-1/-Q1 is shown in Figure 34. TI recommends connecting the IN, Gate and
OUT pins close to the source and drain pins of the MOSFET. Keep the traces of the MOSFET drain wide and
short to minimize resistive losses. Place surge suppressors (D1 and D4) components as shown in the example
layout of LM5050-1 in Layout Example.
10.2 Layout Example
Figure 34. Typical Layout Example With D2PAK N-MOSFET
Copyright © 2011–2015, Texas Instruments Incorporated
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Product Folder Links: LM5050-1 LM5050-1-Q1



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