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RF430CL331HIPWR bảng dữ liệu(PDF) 44 Page - Texas Instruments |
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RF430CL331HIPWR bảng dữ liệu(HTML) 44 Page - Texas Instruments |
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44 / 60 page ![]() RF430CL331H SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015 www.ti.com 5.11.8 Host Response Register This register is used, after an interrupt is asserted by the RF430CL331H. It communicates various responses from the host controller. The actual interrupt flag clearing must happen immediately before setting the response in this register. Table 5-31. Host Response Register ADDRESS 15 14 13 12 11 10 9 8 0xFFEB Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ADDRESS 7 6 5 4 3 2 1 0 Use Custom Extra Data Interrupt 0xFFEA Reserved Reserved Reserved Reserved SW File Exists Sent In Serviced Response Table 5-32. Host Response Register Description BIT FIELD TYPE RESET DESCRIPTION 15-4 Reserved R/W 0 Reserved for future use. Write with 0. This may only be set if the Read Prefetch interrupt has been asserted. This is possible only after a Read Binary command. This indicates to the RF430CL331H that extra data has been written to the buffer during RF data transmission to a previous Read Binary command. To enable this feature, the 3 Extra Data Sent In R/W 0 Extra Data Interrupt Enable must be set. This also called Prefetch on Read. 0b = No extra data has been written. 1b = Extra data has been written. Update buffer size. This sets whether or not a custom SW (status word) should be responded to a NFC Type 4 command (Select, Read Binary, Update Binary). 2 Use Custom SW Response R/W 0 0b = Default response to the PCD. 1b = Custom response to the PCD. The actual SW response is taken from the Custom SW Response Register. This is the response to the interrupt of General Type 4 Request with status of file select. 1 File Exists R/W 0 0b = File named in the NDEF File Identifier Register does not exist. 1b = File named in the NDEF File Identifier Register does exist. Setting this bit high after an interrupt (this applies only to General Type 4 Requests IRQ) has been asserted by the RF430CL331H indicates that the interrupt has been completely serviced. The actual interrupt flag clearing must happen immediately before setting this register. 0 Interrupt Serviced R/W 0 0b = The interrupt is in the process of being serviced by the host controller 1b = The interrupt has been serviced, RF430CL331H to start processing the response 44 Detailed Description Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: RF430CL331H |
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