XIO2001IPNP datasheet(99/141 Pages) TI1

99 / 141 page

XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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Read-only, Read/Write

Default value:

0000 1340h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Table 71. Secondary Uncorrectable Error Severity Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14

RSVD

Reserved. Returns 00 0000 0000 0000 0000b when read.

13(1)

INTERNAL_ERROR_SEVR

Internal bridge error. This severity bit is associated with a PCI-X error and has no effect

on the bridge.

12(1)

SERR_DETECT_SEVR

SERR assertion detected

0 = Error condition is signaled using ERR_NONFATAL

1 = Error condition is signaled using ERR_FATAL (default)

11(1)

PERR_DETECT_SEVR

PERR assertion detected

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

10(1)

DISCARD_TIMER_SEVR

Delayed transaction discard timer expired

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

9(1)

UNCOR_ADDR_SEVR

Uncorrectable address error

0 = Error condition is signaled using ERR_NONFATAL

1 = Error condition is signaled using ERR_FATAL (default)

8(1)

UNCOR_ATTRIB_SEVR

Uncorrectable attribute error. This severity bit is associated with a PCI-X error and has

no effect on the bridge.

7(1)

UNCOR_DATA_SEVR

Uncorrectable data error

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

6(1)

UNCOR_SPLTMSG_SEVR

Uncorrectable split completion message data error. This severity bit is associated with

a PCI-X error and has no effect on the bridge.

5(1)

UNCOR_SPLTCMP_SEVR

Unexpected split completion error. This severity bit is associated with a PCI-X error and

has no effect on the bridge.

RSVD

Reserved. Returns 0b when read.

3(1)

MASTER_ABORT_SEVR

Received master abort

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

2(1)

TARGET_ABORT_SEVR

Received target aborta

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

1(1)

MABRT_SPLIT_SEVR

Master abort on split completion. This severity bit is associated with a PCI-X error and

has no effect on the bridge.

TABRT_SPLIT_SEVR

Target abort on split completion. This severity bit is associated with a PCI-X error and

has no effect on the bridge.

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