XIO2001IPNP datasheet(62/141 Pages) TI1

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XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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8.4.42 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

PCI register offset:

51h

Read-only

Default value:

70h

BIT NUMBER

RESET STATE

8.4.43 MSI Message Control Register

This register controls the sending of MSI messages. See Table 31 for a complete description of the register

contents.

PCI register offset:

52h

Read-only, Read/Write

Default value:

0088h

BIT NUMBER

RESET STATE

Table 31. MSI Message Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

RSVD

Reserved. Returns 00h when read.

64CAP

64-bit message capability. This bit is read-only 1b indicating that the bridge supports 64-bit

MSI message addressing.

6:4

MM_EN

Multiple message enable. This bit indicates the number of distinct messages that the

bridge is allowed to generate.

000 = 1 message (default)

001 = 2 messages

010 = 4 messages

011 = 8 messages

100 = 16 messages

101 = Reserved

110 = Reserved

111 = Reserved

3:1

MM_CAP

Multiple message capabilities. This field indicates the number of distinct messages that

bridge is capable of generating. This field is read-only 100b indicating that the bridge can

signal 1 interrupt for each IRQ supported on the serial IRQ stream up to a maximum of 16

unique interrupts.

MSI_EN

MSI enable. This bit enables MSI interrupt signaling. MSI signaling must be enabled by

software for the bridge to signal that a serial IRQ has been detected.

0 =

1 =

MSI signaling is prohibited (default)

MSI signaling is enabled

8.4.44 MSI Message Lower Address Register

This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is

detected. See Table 32 for a complete description of the register contents.

PCI register offset:

54h

Read-only, Read/Write

Default value:

0000 0000h

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