SIO1007 datasheet(76/108 Pages) MICROCHIP

76 / 108 page

SIO1007

DS00002020A-page 76

 2005 - 2015 Microchip Technology Inc.

18.4.41

CR2A

CR2A can only be accessed in the configuration state and after the CSR has been initialized to 2AH. CR2A is used to

select the IRQ mapping (bits 0 - 3) for the IRQIN2 pin. The four bit IRQ encoding field is defined in Table 18-32 on

page 74. Any unselected IRQ output (registers CR28 - CR2A) is in tristate. Shared IRQs are not supported in the

SIO1007.

18.4.42

CR2B

CR2B can only be accessed in the configuration state and after the CSR has been initialized to 2BH. CR2B is used to

set the SCE (FIR) base address ADR[10:3].

The SCE (FIR) logical device base address is initialized using the base address bits located in two configuration regis-

ters: CR2B-low byte and CR1E-high byte. The SCE base address can be set to 8160 locations on 8-byte boundaries

from 0000H - FFF8H.

The SCE (FIR) base address bits A[2:0] are decoded as 000b. The SCE (FIR) block uses full 16-bit addressing decod-

ing. An address matching the SCE (FIR) base address bits A[15:3] is decoded using the specific address bits A[2:0] to

target registers in SCE (FIR).

When the SCE (FIR) logical device activate bit CR3A-bit0 is cleared to 0, no address decoding takes place for the SCE

(FIR) logical device.

TABLE 18-35: CR2A

IRQIN2

Type: R/W

Default: 0X00 ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

3:0

IRQIN2

Selects the IRQ for IRQIN2. (See Application Note in the Routable IRQ

Inputs Section 12.2.)

7:4

Reserved

Read Only. A read returns 0.

TABLE 18-36: CR2B

SCE (FIR) Base Address Register - Low Byte

Type: R/W

Default: 0X00 ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

ADR3

FIR Base Address bits for decoder.

ADR4

ADR5

ADR6

ADR7

ADR8

ADR9

ADR10

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