SIO1007 datasheet(63/108 Pages) MICROCHIP

63 / 108 page

 2005 - 2015 Microchip Technology Inc.

DS00002020A-page 63

SIO1007

18.4.10

CR09

CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H. CR09 is a test

control register and all bits must be treated as Reserved.

18.4.11

CR0A

CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH. CR0A Bits [5:4]

are CIRCC2 OUTPUT MUX bits and are reset to the default state by a VTR POR. CR0A Bits [7:6] control the IRCC2

OUTPUT MUX and are reset to the default state by a VTR POR, VCC POR and PCI Reset.

Note:

All test modes are reserved for Microchip use. Activating test mode registers may produce undesired

results.

TABLE 18-9:

CR09

Test 4

Type: R/W

Default: 0X00 ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

Test 24

RESERVED FOR MICROCHIP USE

Test 25

Test 26

Test 27

Test 28

Test 29

Test 30

Test 31

TABLE 18-10: CR0A

IR MUX

Type: R/W

Default: 0x00 on VTR POR;

00xx0000b VCC POR;

Bits[7:6] = 00 on PCI RESET

BIT NO.

BIT NAME

DESCRIPTION

3:0

Reserved

Read Only. A read returns 0.

4,5

CIRCC2 Output

Mux

These bits are used to select CIRCC Output Mux Mode.

BIT5

BIT4

MUX MODE

Default tristate (Note 18-6)

Active device to CIRCC2 port. That is,

use CIRRX, CIRTX (pins 23, 24). When

CIRCC2 is inactive (Power Down bit =

0), then CIRTX pin is low.

Reserved.(Note 18-6)

SIO1007 bảng dữ liệu(PDF) 63 Page - Microchip Technology

SIO1007 bảng dữ liệu(HTML) 63 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL