ADC14X250 datasheet(14/69 Pages) TI1

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VIS

VID

GND

VID = |VI

± VI

VIS = |VI

+ + V

-| / 2

VSS

dVSS/dt

+ referenced to V

VSS = 2*|VI

± VI

+ and V

- referenced to GND

ADC14X250

SLASE49 – DECEMBER 2015

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Timing Requirements (continued)

Unless otherwise noted, these specifications apply for VA3.0= 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS. VSPI =

1.8 V

(1). Typical values are at T

A = 25°C. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tH-SYNCb

SYNCb assertion hold time

Required SYNCb hold time after assertion before de-assertion to

initiate a link re-synchronization.

Frame clock

cycles

tILA

ILA duration

Duration of the ILA sequence .

Multi-frame

clock cycles

SERIAL OUTPUT DATA TIMING CHARACTERISTICS

FSR

Serial bit rate

1.0

5.0

Gb/s

Unit Interval

5.0 Gb/s Data Rate

200

tR, tF

Edge transition rise and fall times

Deterministic jitter

Includes periodic jitter (PJ), data dependent jitter (DDJ), duty cycle

distortion (DCD), and inter-symbol interference (ISI); 5.0 Gb/s data

rate.

0.032

p-p UI

6.33

p-p ps

Random jitter

Assumes BER of 1e-15 (Q = 15.88); 5.0 Gb/s data rate

0.118

p-p UI

1.48

rms ps

Total jitter

Sum of DJ and RJ. Assumes BER of 1e-15 (measured Q = 15.6); 5.0

Gb/s data rate.

0.148

p-p UI

29.56

p-p ps

SPI BUS TIMING CHARACTERISTICS (1)

fSCLK

Serial clock frequency

fSCLK = 1 / tP

MHz

tPH

SCLK pulse width – high

tPL

SCLK pulse width – low

tSSU

SDI input data setup time

tSH

SDI input data hold time

tODZ

SDO output data driven-to-3-state time

tOZD

SDO output data 3-state-to-driven time

tOD

SDO output data delay time

tCSS

CSB setup time

tCSH

CSB hold time

tIAG

Inter-access gap

Minimum time CSB must be de-asserted between accesses

Figure 1. Electrical Level Diagram for Differential Input Signals

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