ADC14X250 datasheet(52/69 Pages) TI1

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ADC14X250

SLASE49 – DECEMBER 2015

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The integrity of the data transfer from the transmitter to receiver is limited by the accuracy of the differential lane

characteristic impedance and the attenuation as the signal travels down the lane. Inaccurate or varying

impedance and frequency dependent attenuation results in increased ISI (part of deterministic jitter) and reduced

signal-to-noise ratio, which limits the ability of the receiver to accurately recover the data.

Two features are provided in the ADC14X250 device serial transmitters to compensate attenuation and ISI

caused by the serial lane: voltage swing control (VOD) and de-emphasis (DEM).

9.1.3.2 Voltage Swing and De-Emphasis Optimization

Voltage swing control (VOD) compensates for attenuation across all frequencies through the channel at the

expense of power consumption. Increasing the voltage swing increases the power consumption. De-emphasis

(DEM) compensates for the frequency dependent attenuation of the channel but results in attenuation at lower

frequencies. The voltage swing control and de-emphasis feature may be used together to optimally compensate

for attenuation effects of the channel.

The frequency response of the PCB channel is typically lowpass with more attenuation occurring at higher

frequencies. The de-emphasis implemented in the ADC14X250 device is a form of linear, continuous-time

equalization that shapes the signal at the transmitter into a high-pass response to counteract the low-pass

response of the channel. The de-emphasis setting should be selected such that the equalizer’s frequency

response is the inverse of the channel’s response. Therefore, transferring data at the highest speeds over long

channel lengths requires knowledge of the channel characteristics.

Optimization of the de-emphasis and voltage swing settings is only necessary if the ISI and losses caused by the

channel are too great for reception at the desired bit rate. Many applications will perform with an adequate BER

using the default settings.

9.1.3.3 Minimizing EMI

High data-transfer rates have the potential to emit radiation. EMI may be minimized using the following

techniques:

•

Use differential stripline channels on inner layer sandwiched between ground layers instead of routing

microstrip pairs on the top layer.

•

Avoid routing lanes near the edges of boards.

•

Enable data scrambling to spread the frequency content of the transmitted data.

•

If the serial lane must travel through an interconnect, choose a connector with good differential pair channels

and shielding.

•

Ensure lanes are designed with an accurate, 100-

Ω characteristic impedance and provide accurate 100-Ω

terminations inside the receiving device.

9.1.4 JESD204B System Considerations

9.1.4.1 Frame and LMFC Clock Alignment Procedure

Frame and LMFC clocks are generated inside the ADC14X250 device and are used to properly align the phase

of the serial data leaving the device. The phases of the frame and multi-frame clocks are determined by the

frame alignment step for JESD204B link initialization as shown in Figure 36. These clocks are not accessible

outside the device. The frequencies of the frame and LMFC must be equal to the frame and LMFC of the device

receiving the serial data.

When the ADC14X250 device is powered-up, the internal frame and local multi-frame clocks initially assume a

default phase alignment. To ensure determinist latency through the JESD204B link, the frame and LMFC clocks

of the ADC14X250 device must be aligned in the system. Perform the following steps to align the ADC14X250

device clocks:

1. Enable the SYSREF signal driver. See SYSREF Signaling for more information.

2. Configure the SYSREF offset feature appropriately based on the SYSREF signal and channel. See

Effectively Using the SYSREF Offset and Detection Gate Features for more information.

3. Enable detection of the SYSREF signal at the ADC14X250 device by enabling the SYSREF detection gate.

4. Apply the desired SYSREF signal at the ADC14X250 device SYSREF input.

5. Disable detection of the SYSREF signal by disabling the SYSREF gate.

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