ADC14X250 datasheet(4/69 Pages) TI1

4 / 69 page

AGND

VA3.0

SYNC+

50:

SYNC-

1k:

2.5V

AGND

2k:

34k:

3pF

1k:

2.5V

VA3.0

SDO

80:

VA3.0

VA1.2

AGND

S+

S-

VA3.0

VA1.2

ADC14X250

SLASE49 – DECEMBER 2015

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Product Folder Links: ADC14X250

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Pin Functions (continued)

TYPE OR DIAGRAM

DESCRIPTION

NAME

NO.

CSB

SPI chip select pin

When this signal is asserted, SCLK is used to clock the

input serial data on the SDI pin or output serial data on

the SDO pin. When this signal is de-asserted, the SDO

pin is high impedance and the input data is ignored.

Active low. A 10 k

Ω pull-up resistor to a supply

corresponding to the CSB drive logic level is

recommended to prevent undesired activation of the

SPI bus. Compatible with 1.2- to 3-V CMOS logic

levels.

SO+

Differential high speed serial data lane pins

These pins must be AC coupled to the receiving

device. The differential trace routing from these pins

must maintain a 100-

Ω characteristic impedance.

SO–

SCLK

SPI serial clock pin

Serial data is shifted into and out of the device

synchronous with this clock signal. Compatible with

1.2- to 3-V CMOS logic levels.

SDI

SPI data input pin

Serial data is shifted into the device on this pin while

the CSB signal is asserted. Compatible with 1.2- to 3-V

CMOS logic levels.

SDO

SPI data output pin

Serial data is shifted out of the device on this pin

during a read command while CSB is asserted. The

output logic level is configurable as 1.2, 1.8, 2.5, or 3

V. The output level must be configured after power up

and before performing a read command. See the

SYNCb+

Differential SYNCb signal input pins

DC coupling is required for coupling the SYNCb signal

to these pins. Each pin is internally terminated to the

DC bias with a large resistor. An internal 100-

differential termination is provided therefore an external

termination is not required. Additional resistive

components in the input structure give the SYNCb

input a wide input common-mode range. The SYNCb

signal is active low and therefore asserted when the

voltage at SYNCb+ is less than at SYNCb–.

If JESD204B sync~ signals are directed via SPI (with

SYNC_SEL=1), then SYNCb+ and SYNCb- may

remain not connected.

SYNCb–

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