ADC14X250 datasheet(46/69 Pages) TI1

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Transmitter

100:-diff

VCMO = 1.2V

VIS = 0.5V

10k:

CLKIN

Receiver

50:

PCB Channel

4*R1*R2 + 200*R1 = 100

R2 / (R1+R2) = 0.5 / VCMO

IDC (Each Side)= VCMO / (R1+R2)

VCMO = 1.2V: R1 = 29.1:, R2 = 20.8: IDC = 24mA

0.1uF

CLKIN

Transmitter

100:-diff

VIS = 0.5V

10k:

CLKIN

Receiver

50:

PCB Channel

ADC14X250

SLASE49 – DECEMBER 2015

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Product Folder Links: ADC14X250

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9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations

Clocking the ADC14X250 device shares many common concepts and system design requirements with

previously released ADC products, but the JESD204B supported architecture adds another layer of complexity to

clocking at the system level. A SYSREF signal accompanies the device clock to provide phase alignment

information for the output data serializer (as well as for the sampling instant when the clock divider is enabled) to

ensure that the latency through the JESD204B link is always known and does not vary, a concept called

deterministic latency. To ensure deterministic latency, the SYSREF signal must meet setup and hold

requirements relative to CLKIN and the design of the clocking interfaces require close attention. As with other

ADCs, the quality of the clock signal also influences the noise and spurious performance of the device.

9.1.2.1 Driving the CLKIN+ and CLKIN– Input

The CLKIN input circuit is composed of a differential receiver and an internal 100-

Ω termination to a weakly

driven common-mode of 0.50 V. TI recommends AC coupling to the CLKIN input with 0.1-uF external capacitors

to maintain the optimal common-mode biasing. Figure 46 shows the CLKIN receiver circuit and an example AC

coupled interface.

Figure 46. Driving the CLKIN Input With an AC Coupled Interface

DC coupling is allowed as long as the input common-mode range requirements are satisfied. The input common-

mode of the CLKIN input is not compatible with many common signaling standards like LVDS and LVPECL.

Therefore, the CLKIN signal driver common-mode must be customized at the transmitter or adjusted along the

interface. Figure 47 shows an example DC coupled interface that uses a resistor divider network to reduce the

common-mode while maintaining a 100-

Ω total termination at the load. Design equations are provided with

example values to determine the resistor values.

Figure 47. Driving the CLKIN Input With an Example DC Coupled Interface

The CLKIN input supports any type of standard signaling that meets the input signal swing and common-mode

range requirements with an appropriate interface. Generic differential sinusoidal or square-wave clock signals are

also supported. TI does not recommend driving the CLKIN input single-ended. The differential lane trace on the

PCB should be designed to be a controlled 100

Ω and protected from noise sources or other signals.

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