TAS5731MPHPR datasheet(50/81 Pages) TI1

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TAS5731M

SLOS838C – JULY 2013 – REVISED AUGUST 2015

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9.6.9 Volume Configuration Register (0x0E)

Bits

Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the

D2–D0:

number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of

the I2S data as follows

Sample Rate (KHz)

Approximate Ramp Rate

8/16/32

125 µs/step

11.025/22.05/44.1

90.7 µs/step

12/24/48

83.3 µs/step

Table 12. Volume Control Register (0x0E)

FUNCTION

–

Reserved(1)

–

Subchannel (ch4) volume = ch1 volume (2) (1)

–

Subchannel volume = register 0x0A(2)

–

Ch3 volume = ch2 volume(1)

–

Ch3 volume = register 0x0A

–

Volume slew 512 steps (43-ms volume ramp time at 48 kHz)

–

Volume slew 1024 steps (85-ms volume ramp time at 48 kHz) (1)

–

Volume slew 2048 steps (171- ms volume ramp time at 48 kHz)

–

Volume slew 256 steps (21-ms volume ramp time at 48 kHz)

–

Reserved

(1)

Default values are in bold.

(2)

Bits 6:5 can be changed only when volume is in MUTE [master volume = MUTE (register 0x07 = 0xFF)].

9.6.10 Modulation Limit Register (0x10)

The modulation limit is the maximum duty cycle of the PWM output waveform.

Table 13. Modulation Limit Register (0x10)

MODULATION LIMIT

–

99.2%

–

98.4%

–

97.7%(1)

–

96.9%

–

96.1%

–

95.3%

–

94.5%

–

93.8%

–

Reserved

(1)

Default values are in bold.

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