Z8018233FSC datasheet(26/109 Pages) ZILOG

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Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Z80182 MIMIC DOUBLE BUFFERING FOR THE TRANSMITTER

The Z80182 Rev DA implements double buffering for the

transmitter in 16450 mode and sets the TEMT bit in the LSR

When this feature is enabled and character delay emulation

is being used (see Figure 9):

The PC THRE bit in the LSR Register is set when the

THR Register is empty;

PC Host writes to the 16450 THR Register;

Whenever the Z80182 TSR buffer is empty and one

character delay timer is in a timed-out state, the byte

from the THR Register is transferred to the TSR buffer;

the timer is in timed-out state after FIFO Reset or after

Host TEMT is set. This allows a dual write to THR when

Host TEMT is set.

Restart character delay timer (timer reloads and counts

down) with byte transfer from THR Register to the TSR

buffer;

Whenever the TSR buffer is full, the TEMT bit in MPU

LSR Register is reset with no delay;

MPU reads TSR buffer;

TEMT bit in LSR Register for MPU is set with no delay

whenever the TSR buffer is empty;

When the TSR buffer is read by MPU and THR Register

is empty and one character delay timer reaches zero,

the TEMT bit in the LSR Register for Host is set from 0

to 1.

The PC THRE bit in the LSR Register is reset whenever the

THR Register is full and set whenever THR Register is

empty.

MPU IREQ and DMA Request for the transmit data is

trigger whenever TSR buffer is full and cleared whenever

TSR buffer is empty.

If character delay emulation is not used the TEMT bit in the

LSR Register is set whenever both the THR Register and

the TSR buffer are both empty. The Host TEMT bit is clear

if there is data in either the TSR buffer of THR Register.

16450

THR

Host Write

Empty/Full

Host & MPU THRE = 1

Byte Transfer if:

- THRE=0;

- TSR = 1;

- Character delay timer is timed out.

Note: Timer reloads and counts down

whenever data is transferred from THR to TSR.

THR to TSR

delay

transfer

TSR

Transmit

Shift Reg.

Emulation

Empty/Full

(MPU TEMT) TSRE = 1

Host TEMT = 1 if - THRE = 1

- TSRE = 1

- Emulation delay timer is timed out

Note: MPU sees TSR bit in the LSR Register as TEMT bit

Added TSR Buffer for the

transmit data

Figure 9. TEMT Emulation Logic Implementation

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