Z8018233FSC datasheet(23/109 Pages) ZILOG

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DS971820600

Table 6. 16550 Line Status Register

Error

Description

How to Set

How to Clear

Error in

At least one data byte available

At least one error in receiver

When there are no more

RCVR

in FIFO with one error

FIFO

errors

FIFO

*TEMT

Transmitter empty

MPU writes a 1

MPU writes a 0

† *THRE

Transmitter holding

When MPU has

When holding register

read or emptied

is not empty

the holding register

Break

Break occurs when

MPU writes 1

There is a

Detect

received data input

PC-side read

is held in logic-0

of the LSR

for longer than a

full word transmission

Framing

Received character

MPU writes 1

There is a

Error

did not have a valid

PC-side read

stop bit

of the LSR

Parity

Received character

MPU writes 1

There is a

Error

did not have correct

PC-side read

even or odd parity

of the LSR

Overrun

Overlapping received

MPU makes

There is a

Error

characters, thereby

two writes

PC-side read

destroying the

to receiver

of the LSR

previous character

buffer register

†Data

Indicates complete

MPU writes to

Empty Receiver

Ready

incoming data has

RCVR FIFO or

or Receiver FIFO

been received

receiver buffer

Notes:

* The TEMT and THRE bits take on different functions when

TEMT/Double Buffer mode is enabled.

† These signals are delayed to HOST when using character

emulation delay.

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