AR0130CSSC00SPBA0-DP datasheet(42/53 Pages) ONSEMI

42 / 53 page

AR0130 DS Rev. L Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

AR0130: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

I/O Timing

By default, the AR0130 launches pixel data, FV, and LV with the falling edge of PIXCLK.

The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of

PIXCLK.

See Figure 31 and Table 9 below and Table 10 on page 43 for I/O timing (AC) characteris-

tics.

Figure 31:

I/O Timing Diagram

Table 9:

I/O Timing Characteristics (2.8V VDD_IO)1

Conditions: fPIXCLK=74.25MHz (720P60fps) VDD_IO=2.8V;

slew rate setting = 4 for PIXCLK; slew rate setting = 7 for parallel ports

Symbol

Definition

Condition

Min

Typ

Max

Unit

fEXTCLK

Input clock frequency

PLL enabled

MHz

tEXTCLK

Input clock period

PLL enabled

166

Input clock rise time

3ns

Input clock fall time

3ns

Input clock duty cycle

tJITTER2

Input clock jitter at 27 MHz

600

tCP

EXTCLK to PIXCLK propagation delay Nominal voltages, PLL Disabled, slew setting =4

tPIXCLK

PIXCLK frequency2

74.25

tRP

PIXCLK rise time

Slew rate setting = 4

1.60

2.70

7.50

tFP

PIXCLK fall time

Slew rate setting = 4

1.50

2.60

7.20

PIXCLK duty cycle

PLL enabled

tPIXJITTER Jitter on PIXCLK

1ns

tPD

PIXCLK to Data[11:0]

PIXCLK slew rate = 4

Parallel slew rate = 7

-2.5

3.5

tPFH

PIXCLK to FV HIGH

PIXCLK slew rate = 4

Parallel slew rate = 7

-2.5

0.5

tPLH

PIXCLK to LV HIGH

PIXCLK slew rate = 4

Parallel slew rate = 7

-3.0

0.0

Data[11:0]

LINE_VALID/

PIXCLK

EXTCLK

tEXTCLK

FRAME_VALID leads LINE_VALID by 6 PIXCLKs.

FRAME_VALID trails

LINE_VALID by 6 PIXCLKs.

tPLH

tPFH

tPFL

tPLL

tPD

Pxl _0

Pxl _1

Pxl _2

Pxl _n

90%

10%

tRP

tFP

90%

10%

FRAME_VALID

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