AR0130CSSC00SPBA0-DP datasheet(41/53 Pages) ONSEMI

41 / 53 page

AR0130 DS Rev. L Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

AR0130: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Notes:

1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

2. Two-wire control is I2C-compatible.

3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXTCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the

undefined region of the falling edge of SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of

the SCLK signal.

6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement

tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch

the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it

must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according

to the Standard-mode I2C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

Table 8:

Two-Wire Serial Bus Characteristics

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; TA = 25°C

Parameter

Symbol

Standard-Mode

Fast-Mode

Unit

Min

Max

Min

Max

SCLK Clock Frequency

fSCL

100

400

KHz

After this period, the first clock pulse is

generated

tHD;STA

4.0

0.6

s

LOW period of the SCLK clock

tLOW

4.7

1.3

s

HIGH period of the SCLK clock

tHIGH

4.0

0.6

s

Set-up time for a repeated START

condition

tSU;STA

4.7

0.6

s

Data hold time:

tHD;DAT

3.455

0.95

s

Data set-up time

tSU;DAT

250

1006

-ns

Rise time of both SDATA and SCLK signals

1000

20 + 0.1Cb7

300

Fall time of both SDATA and SCLK signals

300

20 + 0.1Cb7

300

Set-up time for STOP condition

tSU;STO

4.0

0.6

s

Bus free time between a STOP and START

condition

tBUF

4.7

1.3

s

Capacitive load for each bus line

400

Serial interface input pin capacitance

CIN_SI

3.3

SDATA max load capacitance

CLOAD_SD

SDATA pull-up resistor

RSD

1.5

4.7

1.5

4.7

K

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