RFM219SW

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For those which are cleared by the MCU, each of them has an ‘EN’ bit and a ‘CLR’ register bit. For example, the Sync Word

detection pass interrupt is only enabled when the ‘SYNC_PS_EN’ bit is set to 1, and the interrupt is cleared by setting the

‘SYNC_PS_CLR’ bit to 1. The MCU does not need to set the ‘SYNC_PS_CLR’ bit back to 0 after setting it to 1, because this bit

automatically clears itself once the interrupt is cleared.

The number of available interrupts and their mappings are different in direct mode and buffer mode. For more details of the GPO

controls, please refer to chapter 5.11 User Registers.

5.9 Data Handling

A data path consists of a packet handler and a 32-byte FIFO which is responsible for delivering the data from the demodulator to

the external MCU. It supports 3 data access modes: direct, buffer and packet mode.

5.9.1 Direct Mode

In direct mode, the data from the demodulator’s output is directly sent out to the MCU via the DOUT, which can be mapped to

GPO 1, 3 or 4. The synchronization clock is output via the DCLK, which can be mapped to GPO 2 or 4. The optional preamble

and sync word detection interrupts are supported upon requirements.

EEPROM (Optional)

RF

DEMOD

clock

1

data

1

Preamble

(Optional)

Sync

(Optional)

User Registers

clock

1

data

1

SPI

DCLK

CSB

SCL

SDA

INT1/INT2

DOUT

Figure 20. Data Path of Direct Mode

The data receiving works independently of the preamble and sync word detection in the direct mode. This means, no matter

whether a valid preamble or a sync word is detected or not, the demodulated data will be transparently output on the DOUT.

The sync clock is generated with two purposes: removing the glitches exist on the data output, and assisting the external MCU to

sample the data at the correct instance.

1 Symbol

Raw Data

Internal

Sync Clock

Output Data

Output

Sync Clock

Figure 21. Demodulated Data and Sync Clock Timing Characteristics