RFM219SW

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Rev 1.0 | Page 15/35

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5.5 Internal Blocks Description

5.5.1 RF Front-end and AGC

The RFM219SW features a low-IF receiver. The RF front-end of the receiver consists of a Low Noise Amplifier (LNA), I/Q

mixer and a wide-band power detector. Only a low-cost inductor and a capacitor are required for matching the LNA to any

common used antennas. The input RF signal induced on the antenna is amplified and down-converted to the IF frequency for

further processing.

By means of the wide-band power detector and the attenuation networks built around the LNA, the Automatic Gain Control (AGC)

loop regulates the RF front-end’s gain to get the best system linearity, selectivity and sensitivity performance, even though the

receiver suffers from strong out-of-band interference.

5.5.2 IF Filter

The signals coming from the RF front-end are filtered by the fully integrated 3

achieves over 35 dB image rejection ratio typically. The IF center frequency is dynamically adjusted to enable the IF filter to

locate to the right frequency band, thus the receiver sensitivity and out-of-band interference attenuation performance are kept

optimal despite the manufacturing process tolerances. The IF bandwidth is automatically computed according to the three basic

system parameters input from the RFPDK: RF frequency, Xtal tolerance, and symbol rate.

5.5.3 RSSI

The subsequent multistage I/Q Log amplifiers enhance the output signal from IF filter before it is fed for demodulation. Receive

Signal Strength Indicator (RSSI) generators are included in both Log amplifiers which produce DC voltages that are directly

proportional to the input signal level in both of I and Q path. The resulting RSSI is a sum of both these two paths. Extending from

the nominal sensitivity level, the RSSI achieves over 66 dB dynamic range.

The RFM219SW integrates a patented DC-offset cancellation engine. The receiver sensitivity performance benefits a lot from

the novel, fast and accurate DC-offset removal implementation.

5.5.4 SAR ADC

The on-chip 8-bit SAR ADC digitalizes the RSSI output. When receiving a FSK or GFSK modulated signal, the digitized RSSI is

used to turn on and off the (G)FSK demodulator. When receiving an OOK modulated signal, it is used for OOK demodulation in

the digital domain.

5.5.5 Crystal Oscillator

The crystal oscillator is used as the reference clock for the PLL frequency synthesizer and system clock for the digital blocks. A

26 MHz crystal should be used with appropriate loading capacitors (C2 and C3 in Figure 9, Page 11). The values of the loading

1

1

+

1

The parasitic capacitance is constituted by the input capacitance and PCB tray capacitance. The ESR of the crystal should be

within the specification in order to ensure a reliable start-up. An external signal source can easily be used in place of a

conventional XTAL and should be connected to the XIN pin. The incoming clock signal is recommended to have a peak-to-peak

swing in the range of 300 mV to 700 mV and AC-coupled to the XIN pin.