PIC16C745SLASHP datasheet(97/158 Pages) MICROCHIP

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DS41124A-page 97

PIC16C745/765

13.2.4

EXTERNAL CLOCK IN

In EC mode, users may directly drive the PIC16C745/

765 provided that this external clock source meets the

AC/DC timing requirements listed in Section 17.4.

Figure 13-2 below shows how an external clock circuit

should be configured.

FIGURE 13-2: EXTERNAL CLOCK INPUT

OPERATION (EC OSC

CONFIGURATION)

13.2.5

E4 MODE

In E4 mode, a PLL module is switched on in-line with

the clock provided to OSC1. The output of the PLL

drives FINT.

FIGURE 13-3: OSCILLATOR/PLL CLOCK CONTROL

13.3

Reset

The PIC16CXX differentiates between various kinds of

reset:

• Power-on Reset (POR)

•MCLR reset during normal operation

•MCLR reset during SLEEP

• WDT Reset (normal operation)

• Brown-out Reset (BOR)

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a “reset

state” on POR, on the MCLR and WDT Reset, on

MCLR reset during SLEEP, and on BOR. The TO and

PD bits are set or cleared differently in different reset

situations as indicated in Table 13-4. These bits are

used in software to determine the nature of the reset.

See Table 13-7 for a full description of reset states of all

registers.

A simplified block diagram of the on-chip reset circuit is

shown in Figure 13-4.

The PICmicro® devices have a MCLR noise filter in the

MCLR reset path. The filter will detect and ignore small

pulses.

It should be noted that a WDT reset does not drive

MCLR pin low.

Clock from

ext. system

PIC16C745/765

OSC1

OSC2/CLKOUT

CLKOUT

Note: CLKOUT is the same frequency as OSC1 if

in E4 mode, otherwise CLKOUT = OSC1/4.

OSC2

OSC1

4x PLL

6 MHz

Q Clock

Generator

To Circuits

24 MHz

FINT

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