DB929B datasheet(23/51 Pages) CMLMICRO

23 / 51 page

4-Level FSK Modem Data Pump

Page 23 of 50

MX929B PRELIMINARY INFORMATION

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from Task 2

from Task 3

from Task 1

Task to Command Register

Data to Data Block Buffer

Modem Tx Output

Symbols to RRC Filter

IBEMPTY Bit

BFREE Bit

Figure 11: Transmit Task Timing Diagram

for Task 2

for Task 3

for Task 1

Task to Command Register

Data from Data Block Buffer

Modem Rx Input

Symbols to De-Interleave

Circuit

BFREE Bit

Figure 12: Receive Task Timing Diagram

4.5.2.22 RRC Filter Delay

The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the

input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times

through to the RRC filter in both transmit and receive modes, as illustrated below:

Delay from Rx Input

(from FM discriminator)

to interpreted data in

internal buffer.

RX Symbol to De-Interleave Buffer

Tx Symbol at TXOUT pin / Rx Symbol from FM discriminator

Symbol-times

Tx Symbol to RRC Filter

Delay from Tx Input

symbol to TXOUT

response.

Figure 13: RRC Low Pass Filter Delay

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