DB929B datasheet(34/51 Pages) CMLMICRO

34 / 51 page

4-Level FSK Modem Data Pump

Page 34 of 50

MX929B PRELIMINARY INFORMATION

www.mxcom.com Tel: 800 638 5577 336 744 5050

Fax: 336 744 5054

Doc. # 20480171.003

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

All trademarks and service marks are held by their respective companies.

Note: during this time the µC may

perform other functions, as the

µC variable 'STATE' is updated

by the interrupt service routine

Disable µC's MX929B Tx Interrupt Service Routine

Enable µC's MX929B Tx Interrupt Service Routine

Set µC variable 'STATE' to 0

Set the Mode Register IRQEN bit to '1'

Set the Mode Register IRQEN bit to '0'

Read the Status Register

Write a RESET task to the Command Register

Set µC variable 'IBLOCKS'

to the number of Intermediate blocks

to be transmitted

Ensure that the Control Register

has been loaded with

a suitable CKDIV value

Write a T24S task to the Command Register

Write 6 bytes of Symbol Sync

pattern to the Data Buffer

Ensure that the Mode Register

IRQEN, PSAVE, RXEYE and SSIEN bits are '0',

the TX/

bit is '1'

and the INVSYM and SSYM bits are

set appropriately

Yes

END

with error

END

START

'STATE' < 6 ?

BFREE bit = 1 ?

'STATE' = 6 ?

Figure 19: Transmit Frame Example Flowchart, Main Program

Notes:

1. The RESET command in Figure 19 and the practice of disabling the MX929B’s

IRQ output when not

needed are not essential but can eliminate problems during debugging and if errors occur in operation

2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command

DB929B bảng dữ liệu(PDF) 34 Page - CML Microcircuits

DB929B bảng dữ liệu(HTML) 34 Page - CML Microcircuits

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

bảng dữ liệu tải về

Link URL