AN4031 datasheet(28/36 Pages) STMICROELECTRONICS

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How to predict DMA latencies

AN4031

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Where:

•

TSM is the total timing for DMA memory port access and transfer which is equal to:

TSM = tMA+ tMAC + tBMA + tSRAM

Where:

3.1.2

DMA transfer time versus concurrent access

Additional latency can be added to the DMA service timing described in Section 3.1.1 when

several masters try to access simultaneously to the same slave.

For peripheral and memory worst-case access/transfer time, the following factors impact the

total delay time for DMA stream service:

•

When several masters are accessing the same AHB destination simultaneously, the

DMA latency is impacted; the DMA transfer cannot start until the bus matrix arbiter

grants access to the DMA as described in Section 2.1.2.

•

When several masters (DMA and CPU) are accessing the same AHB-to-APB bridge,

the DMA transfer time is delayed due to the AHB-to-APB bridge arbitration as

described in Section 2.3.2.

Table 7. Peripheral port access/transfer time versus DMA path used

Description

Through bus matrix

DMA’s

direct paths

To AHB

peripherals

To APB

peripherals

tPA: DMA peripheral port arbitration

1 AHB cycle

tPAC: peripheral address computation

1 AHB cycle

tBMA: bus matrix arbitration (when no

concurrency)(1)

1. In the case of STM32F401, tBMA is equal to zero.

1 AHB cycle

N/A

tEDT: effective data transfer

1 AHB cycle(2) (3)

2. For FMC, an additional cycle can be added depending on the external memory used. Additional AHB

cycles are added depending on external memory timings.

3. In case of burst, the effective data transfer time depends on the burst length (INC4 tEDT= 4 AHB cycles).

2 APB cycles

2 APB cycle

tBS: bus synchronization

N/A

1 AHB cycle

Table 8. Memory port access/transfer time

Description

Latency

tMA: DMA memory port arbitration

1 AHB cycle

tMAC: memory address computation

1 AHB cycle

tBMA: bus matrix arbitration (when no concurrency)(1)

1. In the case of STM32F401, tBMA is equal to zero.

1 AHB cycle(2)

2. For consecutive SRAM accesses (while no other master accesses the same SRAM in-between),

tBMA = 0 cycle.

tSRAM: SRAM read or write access

1 AHB cycle

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